Error rate-based wear-leveling for nand flash memory at highly scaled technology nodes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 21, Issue 7, 2013, Pages 1350-1354

  Pan, Yangyang ^a   Dong, Guiqiang ^a   Zhang, Tong ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

Error rate; process variation; solid state drive; wear leveling

Indexed keywords

CONVENTIONAL DESIGN; ERROR RATE; PROCESS VARIATION; RAW BIT ERROR RATES; SCALED TECHNOLOGIES; SOLID STATE DRIVES; WEAR LEVELING; WEAR-LEVELING ALGORITHMS;

ALGORITHMS; NAND CIRCUITS;

FLASH MEMORY;

EID: 84880068800     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2012.2210256     Document Type: Article

References (14)

1. H. Choi, W. Liu, and W. Sung, "VLSI implementation of BCH error correction for multilevel cell NAND Flash memory," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 5, pp. 843-847, May 2010.
2. C. Yang, Y. Emre, and C. Chakrabarti, "Product code schemes for error correction in MLC NAND Flash memories," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 12, pp. 2302-2314, 2012.
3. E. Gal and S. Toledo, "Algorithms and data structures for Flash memories," ACM Comput. Surv., vol. 37, no. 2, pp. 138-163, 2005. (Pubitemid 41527575)
4. A. B. Aroya and S. Toledo, "Competitive analysis of Flash-memory algorithms," in Proc. Ann. Eur. Symp., 2006, pp. 100-111. (Pubitemid 44699645)
5. M. Wu and W. Zwaenepoel, "eNVy: A nonvolatile main memory storage system," in Proc. 14th Workshop Workstation Operat. Syst., Oct. 1993, pp. 116-118.
6. L.-P. Chang, T.-W. Kuo, and S.-W. Lo, "Real-time garbage collection for Flash-memory storage systems of real-time embedded systems," ACM Trans. Embed. Comput. Syst., vol. 3, no. 4, pp. 837-863, 2004.
7. M.-L. Chiang and R.-C. Chang, "Cleaning policies in mobile computers using Flash memory," J. Syst. Softw., vol. 48, no. 3, pp. 213-231, 1999. (Pubitemid 30501608)
8. H. Kim and S. Lee, "An effective Flash memory manager for reliable Flash memory space management," IEICE Trans. Inform. Syst., vol. 85, no. 6, pp. 950-964, 2002. (Pubitemid 34962538)
9. N. Agrawal, V. Prabhakaran, T. Wobber, J. D. Davis, M. Manasse, and R. Panigrahy, "Design tradeoffs for SSD performance," in Proc. USENIX Ann. Tech. Conf., 2008, pp. 57-70.
10. J.-W. Hsieh, T.-W. Kuo, and L.-P. Chang, "Efficient identification of hot data for Flash memory storage systems," ACM Trans. Storage, vol. 2, no. 1, pp. 22-40, Feb. 2006. (Pubitemid 43925124)
11. A. Spessot, A. Calderoni, P. Fantini, A. S. Spinelli, C. M. Compagnoni, F. Farina, A. L. Lacaita, and A. Marmiroli, "Variability effects on the VT distribution of nanoscale NAND Flash memories," in Proc. IEEE Int. Rel. Phys. Symp., May 2010, pp. 970-974.
12. J. Fitzpatrick, "Flash secrets revealed," in Proc. Flash Memory SUMMIT, Aug. 2010.
13. J. S. Bucy, J. Schindler, S. W. Schlosser, and G. R. Ganger, "The disksim simulation environment version 4.0 reference manual," Carnegie Mellon Univ., Pittsburgh, PA, Rep. CMU-PDL-08-101, May 2008.
14. Open NAND Flash Interface Specification (2011). [Online]. Available: http://onfi.org/