메뉴 건너뛰기




Volumn , Issue , 2009, Pages 23-32

Choose-your-own-adventure routing: Lightweight load-time defect avoidance

Author keywords

Algorithms; Alternatives; Bitstream load; Defect tolerance; Design; Experimentation; In field repair; Programmable interconnect; Reliability

Indexed keywords

ALTERNATIVES; BITSTREAM LOAD; DEFECT TOLERANCE; EXPERIMENTATION; IN-FIELD REPAIR; PROGRAMMABLE INTERCONNECT;

EID: 67650705068     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1508128.1508133     Document Type: Conference Paper
Times cited : (14)

References (36)
  • 3
    • 1842582489 scopus 로고    scopus 로고
    • Making typical silicon matter with Razor
    • T. Austin, D. Blaauw, T. Mudge, and K. Flautner. Making typical silicon matter with Razor. IEEE Computer, 37(3):57-65, March 2004.
    • (2004) IEEE Computer , vol.37 , Issue.3 , pp. 57-65
    • Austin, T.1    Blaauw, D.2    Mudge, T.3    Flautner, K.4
  • 5
    • 84869531893 scopus 로고    scopus 로고
    • VPR and T-VPack: Versatile packing
    • V. Betz. VPR and T-VPack: Versatile Packing, Placement and Routing for FPGAs.http: //www.eecg.toronto.edu/~vaughn/vpr/vpr.html, March 27 1999. Version 4.30.
    • (1999) Placement and Routing for FPGAs
    • Betz, V.1
  • 8
    • 33846118079 scopus 로고    scopus 로고
    • Designing reliable systems from unreliable components: the challenges of transistor variability and degradation
    • S. Borkar. Designing reliable systems from unreliable components: the challenges of transistor variability and degradation. IEEE Micro, 25(6):10-16, November-December 2005.
    • (2005) IEEE Micro , vol.25 , Issue.6
    • Borkar, S.1
  • 9
    • 33745808576 scopus 로고    scopus 로고
    • Yield modelling and yield enhancement for FPGAs using fault tolerance schemes
    • N. Campregher, P. Y. K. Cheung, G. A. Constantinides, and M. Vasilko. Yield modelling and yield enhancement for FPGAs using fault tolerance schemes. In FPL, 2005.
    • (2005) FPL
    • Campregher, N.1    Cheung, P.Y.K.2    Constantinides, G.A.3    Vasilko, M.4
  • 10
    • 46249102184 scopus 로고    scopus 로고
    • Reconfiguration and fine-grained redundancy for fault tolerance in FPGAs
    • N. Campregher, P. Y. K. Cheung, G. A. Constantinides, and M. Vasilko. Reconfiguration and fine-grained redundancy for fault tolerance in FPGAs. In FPL, 2006.
    • (2006) FPL
    • Campregher, N.1    Cheung, P.Y.K.2    Constantinides, G.A.3    Vasilko, M.4
  • 11
    • 67650694354 scopus 로고
    • Programmable logic devices with spare circuits for replacement of defects
    • R. G. Cliff, R. Raman, and S. T. Reddy. Programmable logic devices with spare circuits for replacement of defects. United States Patent Number: 5,434,514, July 18 1995.
    • (1995) United States Patent Number , vol.5 , Issue.434 , pp. 514
    • Cliff, R.G.1    Raman, R.2    Reddy, S.T.3
  • 13
    • 34547879755 scopus 로고    scopus 로고
    • Java based interface for reconfigurable computing
    • S. Guccione, D. Levi, and P. Sundararajan. JBits: Java based interface for reconfigurable computing. In Proc. MAPLD, 1999.
    • (1999) Proc. MAPLD
    • Guccione, S.1    Levi, D.2    Sundararajan, P.3
  • 14
    • 33847130112 scopus 로고    scopus 로고
    • A yield and speed enhancement scheme under within-die variations on 90nm LUT array
    • K. Katsuki, M. Kotani, K. Kobayashi, and H. Onodera. A yield and speed enhancement scheme under within-die variations on 90nm LUT array. In CICC, pages 601-604, 2005.
    • (2005) CICC , pp. 601-604
    • Katsuki, K.1    Kotani, M.2    Kobayashi, K.3    Onodera, H.4
  • 15
    • 0031623057 scopus 로고    scopus 로고
    • Efficiently supporting fault-tolerance in FPGAs
    • J. Lach, W. H. Mangione-Smith, and M. Potkonjak. Efficiently Supporting Fault-Tolerance in FPGAs. In FPGA, pages 105-115, February 1998.
    • (1998) FPGA , pp. 105-115
    • Lach, J.1    Mangione-Smith, W.H.2    Potkonjak, M.3
  • 20
    • 0029204986 scopus 로고
    • A negotiation-based performance-driven router for FPGAs
    • L. McMurchie and C. Ebeling. PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs. In FPGA, pages 111-117. ACM, February 1995.
    • (1995) FPGA , pp. 111-117
    • McMurchie, L.1    Ebeling, C.2
  • 23
    • 85016058885 scopus 로고    scopus 로고
    • Parametric yield modeling and simulations of FPGA circuits considering within-die delay variations
    • P. Sedcole and P. Y. K. Cheung. Parametric yield modeling and simulations of FPGA circuits considering within-die delay variations. ACM Tr. Reconfig. Tech. and Sys., 1(2), June 2008.
    • (2008) ACM Tr. Reconfig. Tech. and Sys , vol.1 , Issue.2
    • Sedcole, P.1    Cheung, P.Y.K.2
  • 24
    • 67650668087 scopus 로고    scopus 로고
    • Enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spirals
    • K. So. Enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spirals. In FPGA, pages 24-33, 2008.
    • (2008) FPGA , pp. 24-33
    • So, K.1
  • 26
    • 0031638178 scopus 로고    scopus 로고
    • A Fast Routability-Driven Router for FPGAs
    • ACM/SIGDA, February
    • J. S. Swarz, V. Betz, and J. Rose. A Fast Routability-Driven Router for FPGAs. In FPGA, pages 140-149. ACM/SIGDA, February 1998.
    • (1998) FPGA , pp. 140-149
    • Swarz, J.S.1    Betz, V.2    Rose, J.3
  • 31
    • 67650661249 scopus 로고    scopus 로고
    • 2100 Logic Drive, San Jose, CA 95124.XC6200 FPGA, version 1.0 edition, June ,Xilinx Inc.
    • Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. XC6200 FPGA Advanced Product Specification, version 1.0 edition, June 1996.
    • (1996) Advanced Product Specification
  • 32
    • 84869546637 scopus 로고    scopus 로고
    • Xilinx Inc. 2100 Logic Drive San Jose CA 95124. Xilinx Virtex-II 1.5V, July
    • Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Xilinx Virtex-II 1.5V Platform FPGAs Data Sheet , July 2002. DS031 .
    • (2002) Platform FPGAs Data Sheet
  • 33
    • 43049122888 scopus 로고    scopus 로고
    • Xilinx Inc. 2100 Logic Drive San Jose CA 95124, June, DS112
    • Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Xilinx Virtex-4 Family Overview, June 2005. DS112 .
    • (2005) Xilinx Virtex-4 Family Overview
  • 34
    • 34247237835 scopus 로고    scopus 로고
    • Xilinx Inc. 2100 Logic Drive San Jose CA 95124, March
    • Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Virtex FPGA Series Configuration and Readback, March 2005. XAPP 138 .
    • (2005) Virtex FPGA Series Configuration and Readback
  • 35
    • 67650683056 scopus 로고    scopus 로고
    • Xilinx Inc. 2100 Logic Drive San Jose CA 95124, September
    • Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Virtex-5 FPGA Configuration User Guide, September 2008. UG191 .
    • (2008) Virtex-5 FPGA Configuration User Guide
  • 36
    • 33745841786 scopus 로고    scopus 로고
    • Defect-tolerant FPGA switch block and connection block with fine-grain redundancy for yield enhancement
    • DOI 10.1109/FPL.2005.1515731, 1515731, Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL
    • A. J. Yu and G. G. Lemieux. Defect-tolerant FPGA switch block and connection block with fine-grain redundancy for yield enhancement. In FPL, pages 255-262, 2005. (Pubitemid 44183442) (Pubitemid 44183442)
    • (2005) Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL , vol.2005 , pp. 255-262
    • Yu, A.J.1    Lemieux, G.G.F.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.