A performance and routability-driven router for fpga's considering path delays

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 2, 1997, Pages 179-185

  Lee, Yuh Sheng ^a   Wu, Allen C H ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Field programmable gate arrays (fpga's); Performance; Routability; Routing

Indexed keywords

ALGORITHMS; INTEGRATED CIRCUIT MANUFACTURE; ITERATIVE METHODS; OPTIMIZATION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

LOGIC GATES;

EID: 0031074191     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.573832     Document Type: Article

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