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Volumn 15, Issue 2, 1998, Pages 65-72

Integrating HDL synthesis and partitioning for multi-FPGA designs

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; LOGIC GATES; SHIFT REGISTERS; TABLE LOOKUP;

EID: 0032047685     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.679209     Document Type: Review
Times cited : (3)

References (11)
  • 2
    • 0026977036 scopus 로고
    • A Tutorial on Logic Synthesis for Lookup-Table Based FPGAs
    • IEEE Computer Society Press, Los Alamitos, Calif.
    • R.J. Francis, "A Tutorial on Logic Synthesis for Lookup-Table Based FPGAs," Proc. Int'l Conf. Computer-Aided Design (IC-CAD), IEEE Computer Society Press, Los Alamitos, Calif., 1992, pp. 40-47.
    • (1992) Proc. Int'l Conf. Computer-Aided Design (IC-CAD) , pp. 40-47
    • Francis, R.J.1
  • 4
    • 0029354779 scopus 로고
    • Recent Directions in Netlist Partitioning: A Survey
    • Elsevier, New York
    • C.J. Alpert and A.B. Kahng, "Recent Directions in Netlist Partitioning: A Survey," Integration: The VLSI Journal, Vol. 19 (1-2), Elsevier, New York, 1995, pp. 1-81.
    • (1995) Integration: The VLSI Journal , vol.19 , Issue.1-2 , pp. 1-81
    • Alpert, C.J.1    Kahng, A.B.2
  • 5
    • 0029528853 scopus 로고
    • Creating Hierarchy in HDL-Based High Density FPGA Design
    • IEEE CS Press
    • C.A. Fields, "Creating Hierarchy in HDL-Based High Density FPGA Design," Proc. Euro-DAC, IEEE CS Press, 1995, pp. 594-599.
    • (1995) Proc. Euro-DAC , pp. 594-599
    • Fields, C.A.1
  • 6
    • 0030387967 scopus 로고    scopus 로고
    • A Hierarchical Functional Structuring and Partitioning Algorithm for Multiple-FPGA Implementations
    • IEEE CS Press
    • W.-J. Fang and A.C.-H. Wu, "A Hierarchical Functional Structuring and Partitioning Algorithm for Multiple-FPGA Implementations," Proc. ICCAD, IEEE CS Press, 1996, pp. 638-643.
    • (1996) Proc. ICCAD , pp. 638-643
    • Fang, W.-J.1    Wu, A.C.-H.2
  • 7
    • 0030679992 scopus 로고    scopus 로고
    • Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy
    • ACM, New York
    • W.-J. Fang and A.C.-H. Wu, "Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy," Proc. 34th Design Automation Conf., ACM, New York, 1997, pp. 518-521.
    • (1997) Proc. 34th Design Automation Conf. , pp. 518-521
    • Fang, W.-J.1    Wu, A.C.-H.2
  • 9
    • 0028570706 scopus 로고
    • Circuit Partitioning for Huge Logic Emulation Systems
    • ACM, New York
    • N.-C. Chou et al., "Circuit Partitioning for Huge Logic Emulation Systems," Proc. 31st Design Automation Conf., ACM, New York, 1994, pp. 244-249.
    • (1994) Proc. 31st Design Automation Conf. , pp. 244-249
    • Chou, N.-C.1
  • 10
    • 85046457769 scopus 로고
    • A Linear Time Heuristic for Improving Network Partitions
    • IEEE CS Press
    • C.M. Fiduccia and R.M. Mattheyses, "A Linear Time Heuristic for Improving Network Partitions," Proc. 19th Design Automation Conf., IEEE CS Press, 1982, pp. 175-181.
    • (1982) Proc. 19th Design Automation Conf. , pp. 175-181
    • Fiduccia, C.M.1    Mattheyses, R.M.2
  • 11
    • 0030672117 scopus 로고    scopus 로고
    • Module Generation of Complex Macros for Logic Emulation Applications
    • ACM, New York
    • W.-J. Fang, A.C.-H. Wu, and D.-P. Chen, "Module Generation of Complex Macros for Logic Emulation Applications," Proc. FPGA 97, ACM, New York, 1997, pp. 69-75.
    • (1997) Proc. FPGA 97 , pp. 69-75
    • Fang, W.-J.1    Wu, A.C.-H.2    Chen, D.-P.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.