Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2012, Pages 279-283

  Chaware, Raghunandan ^a   Nagarajan, Kumar ^a   Ramalingam, Suresh ^a  

^a XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; ASSEMBLY PROCESS; ASSEMBLY TESTS; ASSEMBLY YIELDS; COST-EFFECTIVE SOLUTIONS; DESIGN COMPLEXITY; DIE SIZE; DIE STACKING; HIGH BANDWIDTH; HIGH DENSITY; LOGIC CELLS; LOGIC CIRCUITRY; LOW POWER; MICRO-BUMPS; MOORE LAW; ON CHIPS; RELIABILITY EVALUATION; RELIABILITY TESTING; SCREENING DESIGN; SEMICONDUCTOR INDUSTRY; SILICON INTEGRATION; STACKED DIE PACKAGES; TECHNICAL CHALLENGES; THERMO COMPRESSION BONDING; THREE DIMENSIONS; THROUGH-SILICON-VIA; UNDERFILL FLOW; UNDERFILL PROCESS; UNDERFILLING; UNDERFILLS;

ASSEMBLY; DESIGN; EXPERIMENTS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATION; LOGIC DEVICES; OPTIMIZATION; RELIABILITY; SEMICONDUCTOR DEVICE MANUFACTURE; THERMAL CYCLING; THREE DIMENSIONAL COMPUTER GRAPHICS;

DIES;

EID: 84866883347     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2012.6248841     Document Type: Conference Paper

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