Enhanced device and circuit-level performance benchmarking of graphene nanoribbon field-effect transistor against a Nano-MOSFET with interconnects

Journal of Nanomaterials

Volumn 2014, Issue , 2014, Pages

  Chin, Huei Chaeng ^a   Lim, Cheng Siong ^a   Wong, Weng Soon ^a   Danapalasingam, Kumeresan A ^a   Arora, Vijay K ^a,b   Tan, Michael Loong Peng ^a  

^a UNIVERSITI TEKNOLOGI MALAYSIA   (Malaysia)

^b WILKES UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DRAIN CURRENT; ENERGY EFFICIENCY; MOSFET DEVICES; NANORIBBONS; SPICE; ULSI CIRCUITS;

ALTERNATIVE TECHNOLOGIES; DRAIN-INDUCED BARRIER LOWERING; INTERCONNECT CAPACITANCE; METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR; PERFORMANCE BENCHMARKING; SILICON-BASED ELECTRONICS; SUB-THRESHOLD SWING(SS); ULTRALARGE SCALE INTEGRATION;

BENCHMARKING;

EID: 84899531181     PISSN: 16874110     EISSN: 16874129     Source Type: Journal    
DOI: 10.1155/2014/879813     Document Type: Article

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