A fast, numerical circuit-level model of carbon nanotube transistor

2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH

Volumn , Issue , 2007, Pages 33-37

  Kazmierski, Tom J ^a   Zhou, Dafeng ^a   Al Hashimi, Bashir M ^a  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

DRAIN CURRENT; NUMERICAL MODELS; SPICE; TIMING CIRCUITS;

CARBON NANOTUBE TRANSISTORS; DRAIN-SOURCE CURRENTS; EVALUATION OF INTEGRALS; NEWTON RAPHSON ITERATION; NUMERICAL COMPLEXITY; NUMERICAL INTEGRATIONS; PIECEWISE LINEAR APPROXIMATIONS; THREE ORDERS OF MAGNITUDE;

CARBON NANOTUBES;

EID: 50849124751     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANOARCH.2007.4400855     Document Type: Conference Paper

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