Efficient post-layout power-delay curve generation

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3728 LNCS, Issue , 2005, Pages 393-403

  Vujkovic, Miodrag ^a   Wadkins, David ^a   Sechen, Carl ^a  

^a University of Washington   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONVERGENCE OF NUMERICAL METHODS; DIGITAL CIRCUITS; SCHEDULING; SYSTEMS ANALYSIS; TRANSISTORS;

3D EXTRACTED PARASITICS; POWER-DELAY CURVE GENERATION; TIMING CONVERGENCE; VERILOG/VHDL;

INTEGRATED CIRCUIT LAYOUT;

EID: 33646426096     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11556930_41     Document Type: Conference Paper

References (14)

1. Cheng, C.K.: Timing Closure Using Layout Based Design Process. (www.techonline.com/community/tech_topic/timing_closure/116)
2. Bryant, R., et al.: Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI. Proc. IEEE, Vol. 89, No.3, (2001)
3. Coudert, O.: Timing and Design Closure in Physical Design Flows. Proc. of the International Symposium on Quality Eectronic Design (ISQED) (2002)
4. Hojat, S., Villarrubia, P.: An Integrated Placement and Synthesis Approach for Timing Closure of PowerPC TM Microprocessors. Proc. IEEE Int. Conference on Computer Design (ICCD) (1997) 206-210
5. rd IEEE Int. Work, on SOC for Real-Time Applications (2003)
6. Posluszny, S., et al.: Timing Closure by Design, A High Frequency Microprocessor Design Methodology. Proc. of Design Automation Conf. (DAC) (2000) 712-717
7. Northrop, G., Lu, P.F.: A Semi-Custom Design Flow in High-Performance Microprocessor Design. Proc. of Design Automation Conference (DAC) (2001) 426-431
8. Yoneno, E., Hurat, P.: Power and Performance Optimization of Cell-Based Designs with Intelligent Transistor Sizing and Cell Creation. IEEE/DATC Electronic Design Processes Workshop, Monterey (2001)
9. Hashimoto, M., Onodera, H.: Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design. IEICE Trans. Fund., Vol.E84-A. (2001) 2769-2777
10. Gosti, W., Khatri, S.R., Sangiovanni-Vincentelli, A.L.: Addressing the timing closure problem by integrating logic optimization and placement. IEEE/ACM International Conference on Computer Aided Design (ICCAD) (2001) 224 - 231
11. AMPS User Guide Version W-2004.12, Synopsys (2004)
12. iTools, InternetCAD.com Inc. (2004)
13. Vujkovic, M., Sechen, C.: Optimized Power-Delay Curve Generation for Standard Cell Ics. Proc. Int. Conf. Comp. Aided Design (ICCAD) San Jose (2002)
14. Vujkovic, M., Wadkins, D., Swartz, B., Sechen, C.: Efficient Timing Closure Without Timing Driven Placement and Routing. Proc. Design Automation Conference (DAC) San Diego (2004)