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Volumn 2000-January, Issue , 2000, Pages 222-228

Hurwitz stable reduced order modeling for RLC interconnect trees

Author keywords

[No Author keywords available]

Indexed keywords

FORESTRY; ASYMPTOTIC STABILITY; COMPUTATIONAL METHODS; DISTRIBUTED PARAMETER NETWORKS; LUMPED PARAMETER NETWORKS; MATHEMATICAL MODELS; POLYNOMIALS; TRANSFER FUNCTIONS;

EID: 0034480899     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896478     Document Type: Conference Paper
Times cited : (25)

References (18)
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  • 2
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  • 3
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    • On the stability of moment-matching approximations in asymptotic waveform evaluation
    • June
    • D. F. Anastasakis, N. Gopal, S.Y. Kim, L. T. Pillage, "On the stability of moment-matching approximations in asymptotic waveform evaluation", Proc. ACM/IEEE DAC, June, 1993. pp.367-72.
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    • Anastasakis, D.F.1    Gopal, N.2    Kim, S.Y.3    Pillage, L.T.4
  • 4
    • 0027262846 scopus 로고
    • Fast Approximation of the Transient Response of Lossy Transmission Line Trees
    • June
    • M. Sriram and S. M kahng, "Fast Approximation of the Transient Response of Lossy Transmission Line Trees", Proc. 30th ACM/IEEE DAC., June 1993, pp. 691-6.
    • (1993) Proc. 30th ACM/IEEE DAC , pp. 691-696
    • Sriram, M.1    Kahng, S.M.2
  • 5
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    • Propagation delay in RLC interconnection Networks
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    • Gao, D.S.1    Zhou, D.2
  • 9
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    • Extend moment computation to 2- port circuit representations
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    • F. J. Liu, C. K. Cheng, "Extend Moment Computation to 2- Port Circuit Representations". ACM/IEEE, Proc. 35th DAC, June. 1998.
    • (1998) ACM/IEEE, Proc. 35th DAC
    • Liu, F.J.1    Cheng, C.K.2
  • 10
    • 0032139262 scopus 로고    scopus 로고
    • PRIMA: Passive reduced-order interconnect macromodeling algorithm
    • Aug
    • A. Odabasioglu, M. Celik, L. T. Pileggi, "PRIMA: passive reduced-order interconnect macromodeling algorithm", IEEE Trans, on CAD. vol.17, Aug. 1998. p.645-54.
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    • Odabasioglu, A.1    Celik, M.2    Pileggi, L.T.3
  • 11
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    • Buffer insertion with accurate gate and interconnect delay computation
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    • C. J. Alpert, A. Devgan and S. T. Quay, "Buffer Insertion with Accurate Gate and Interconnect Delay Computation", ACM/IEEE, Proc. DAC, June 1999, pp. 479-84.
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    • Modeling the driving- point characteristic of resistive interconnect for accurate delay Estimation
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.