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1
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0025414182
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Asymptotic waveform evaluation for timing analysis
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L. T. Pillage, R. A. Rohrer, "Asymptotic Waveform Evaluation for Timing Analysis", IEEE Trans, on CAD, Apr.l990, vol 9, p.p. 352-66.
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Pillage, L.T.1
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RICE: Rapid interconnect circuit evaluation using AWE
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Jun
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C. L. Ratzlaff, L. T. Pillage, "RICE: Rapid Interconnect Circuit Evaluation Using AWE", IEEE Trans, on CAD, Jun. 1994, vol 13, p.p. 763-6.
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Ratzlaff, C.L.1
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3
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84949802109
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On the stability of moment-matching approximations in asymptotic waveform evaluation
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June
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D. F. Anastasakis, N. Gopal, S.Y. Kim, L. T. Pillage, "On the stability of moment-matching approximations in asymptotic waveform evaluation", Proc. ACM/IEEE DAC, June, 1993. pp.367-72.
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Proc. ACM/IEEE DAC
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Anastasakis, D.F.1
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Pillage, L.T.4
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4
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0027262846
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Fast Approximation of the Transient Response of Lossy Transmission Line Trees
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June
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M. Sriram and S. M kahng, "Fast Approximation of the Transient Response of Lossy Transmission Line Trees", Proc. 30th ACM/IEEE DAC., June 1993, pp. 691-6.
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Sriram, M.1
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5
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0027225034
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Propagation delay in RLC interconnection Networks
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May
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D. S. Gao, D. Zhou, "Propagation delay in RLC interconnection Networks", Proc. IEEE ISCAS, May 1993. p.2125-8.
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Gao, D.S.1
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0031349694
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An analytical delay model for RLC interconnects
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Dec
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S. Muddu and A. B Khang, "An Analytical Delay Model for RLC Interconnects", IEEE Trans, on Computer-Aided Design of Integrated Circuits and System, Vol.16, No, 12, Dec. 1997.
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Muddu, S.1
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9
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Extend moment computation to 2- port circuit representations
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June
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F. J. Liu, C. K. Cheng, "Extend Moment Computation to 2- Port Circuit Representations". ACM/IEEE, Proc. 35th DAC, June. 1998.
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ACM/IEEE, Proc. 35th DAC
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Liu, F.J.1
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10
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PRIMA: Passive reduced-order interconnect macromodeling algorithm
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Aug
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A. Odabasioglu, M. Celik, L. T. Pileggi, "PRIMA: passive reduced-order interconnect macromodeling algorithm", IEEE Trans, on CAD. vol.17, Aug. 1998. p.645-54.
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Odabasioglu, A.1
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11
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0032650596
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Buffer insertion with accurate gate and interconnect delay computation
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June
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C. J. Alpert, A. Devgan and S. T. Quay, "Buffer Insertion with Accurate Gate and Interconnect Delay Computation", ACM/IEEE, Proc. DAC, June 1999, pp. 479-84.
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Alpert, C.J.1
Devgan, A.2
Quay, S.T.3
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13
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0024906813
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Modeling the driving- point characteristic of resistive interconnect for accurate delay Estimation
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P. R. O'Brien and T. L. Savarino, "Modeling the Driving- Point Characteristic of Resistive Interconnect for Accurate Delay Estimation", Proc. IEEE ICCAD, 1989, pp. 512-5.
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17
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0028756124
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Modeling the effective capacitance for the RC interconnect of CMOS gates
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Dec
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J. Qian; S. Pullela; L. Pillage. "Modeling the Effective capacitance for the RC interconnect of CMOS gates". IEEE Trans, on CAD, vol.13, (no.12), Dec. 1994. pp.1526-35.
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Qian, J.1
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