Post-CMOS processing and 3-D integration based on dry-film lithography

IEEE Transactions on Components, Packaging and Manufacturing Technology

Volumn 3, Issue 9, 2013, Pages 1458-1466

  Temiz, Yuksel ^a   Guiducci, Carlotta ^a   Leblebici, Yusuf ^a  

^a EPFL   (Switzerland)

Author keywords

3 D integration; Die level processing; Dry film lithography; Parylene bonding; Post complementary metal oxide semiconductor (CMOS) processing; Through silicon via (TSV); Via last TSV

Indexed keywords

3-D INTEGRATION; METAL OXIDE SEMICONDUCTORS (CMOS); PARYLENE BONDING; THROUGH-SILICON VIA; VIA-LAST TSV;

AUTOMOBILE MANUFACTURE; ELECTRONICS PACKAGING; ETCHING; INTEGRATION; PASSIVATION; PHOTOLITHOGRAPHY;

BONDING;

EID: 84884291087     PISSN: 21563950     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCPMT.2012.2228004     Document Type: Article

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