Wafer-to-wafer alignment for three-dimensional integration: A review

Journal of Microelectromechanical Systems

Volumn 20, Issue 4, 2011, Pages 885-898

  Lee, Sang Hwui ^a   Chen, Kuan Neng ^b   Lu, James Jian Qiang ^c  

^a LABORATORY FOR PHYSICAL SCIENCES   (United States)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

3 D integration; Alignment; wafer bonding; wafer level packaging

Indexed keywords

3-D INTEGRATED CIRCUIT; 3-D INTEGRATION; ALIGNMENT ACCURACY; ALIGNMENT MECHANISM; ALIGNMENT METHODS; MANUFACTURING TECHNIQUES; PREBONDING; REPRODUCIBILITIES; RESEARCH ACTIVITIES; THERMAL MISMATCH; THREE DIMENSIONAL INTEGRATION; THREE-DIMENSIONAL PROCESS; WAFER ALIGNMENT; WAFER LEVEL; WAFER LEVEL PACKAGING; WAFER-TO-WAFER ALIGNMENT;

ALIGNMENT; INTEGRATION; MANUFACTURE; MEMS; MICROELECTROMECHANICAL DEVICES; MICROELECTRONICS; THREE DIMENSIONAL; WAFER BONDING;

ELECTRONICS PACKAGING;

EID: 79961208644     PISSN: 10577157     EISSN: None     Source Type: Journal    
DOI: 10.1109/JMEMS.2011.2148161     Document Type: Review

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