Wafer-level 3D integration technology

IBM Journal of Research and Development

Volumn 52, Issue 6, 2008, Pages 583-597

  Koester, Steven J ^a   Young, Albert M ^a   Yu, Roy R ^a   Purushothaman, Sampath ^a   Chen, Kuan Neng ^a   La Tulipe Jr , Douglas C ^a   Rana, Narender ^a   Shi, Leathen ^a   Wordeman, Matthew R ^a   Sprogis, Edmund J ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATION;

3-D INTEGRATION; INTEGRATION SCHEME; PROCESS TECHNOLOGIES; PROCESS VARIATION; PRODUCTION ENVIRONMENTS; WAFER-LEVEL 3D INTEGRATION; WAFER-LEVEL INTEGRATION; WAFER-LEVEL THREE-DIMENSIONAL (3D) INTEGRATION;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 61649096165     PISSN: 00188646     EISSN: 00188646     Source Type: Journal    
DOI: 10.1147/JRD.2008.5388565     Document Type: Review

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