3-D wafer-level packaging die stacking using spin-on-dielectric polymer liner through-silicon vias

IEEE Transactions on Components, Packaging and Manufacturing Technology

Volumn 1, Issue 6, 2011, Pages 833-840

  Civale, Yann ^a   Tezcan, Deniz Sabuncuoglu ^a   Philipsen, Harold G G ^a   Duval, Fabrice F C ^a   Jaenen, Patrick ^a   Travaly, Youssef ^a   Soussan, Philippe ^a   Swinnen, Bart ^a   Beyne, Eric ^a  

^a IMEC   (Belgium)

Author keywords

Integrated circuit fabrication; integrated circuit interconnections; integrated circuit packaging; integrated circuits; packaging

Indexed keywords

DIE STACKING; ELECTRICAL CHARACTERIZATION; INTEGRATED CIRCUIT FABRICATION; INTEGRATED CIRCUIT INTERCONNECTIONS; INTEGRATED CIRCUIT PACKAGING; ION ETCHING; MICRO-BUMPS; POLYMER LINERS; PROCESS FLOWS; SI WAFER; THROUGH SILICON VIAS; THROUGH-SILICON-VIA; WAFER LEVEL PACKAGING;

FILLED POLYMERS; INTEGRATED CIRCUITS; PACKAGING; PIPE LININGS; POLYMERS; SILICON; SILICON WAFERS; THREE DIMENSIONAL; WAFER BONDING;

ELECTRONICS PACKAGING;

EID: 84859791884     PISSN: 21563950     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCPMT.2011.2125791     Document Type: Article

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