3D stacked IC demonstrator using hybrid collective die-to-wafer bonding with copper through silicon vias (TSV)

2009 IEEE International Conference on 3D System Integration, 3DIC 2009

Volumn , Issue , 2009, Pages

  Van Olmen, J ^a   Coenen, J ^a   DehaeneW , ^b   De Meyer, K ^b   Huyghebaert, C ^a   Jourdain, A ^a   Katti, Guruprasad ^b   Mercha, A ^a   Rakowski, M ^a   Stucchi, M ^a   Travaly, Y ^a   Beyne, E ^a   Swinnen, B ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

3D CIRCUIT; CMOS PROCESSS; ELECTRICAL CHARACTERIZATION; INTEGRATION ISSUES; POLYMER BONDING; PROCESS DEVELOPMENT; RING OSCILLATOR; THERMO COMPRESSION BONDING; THROUGH SILICON VIAS;

COPPER; DIES; INTERCONNECTION NETWORKS; LANDING; OSCILLATORS (ELECTRONIC); SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; THREE DIMENSIONAL;

WAFER BONDING;

EID: 70549098723     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2009.5306600     Document Type: Conference Paper

References (7)

1. E. Beyne, "3D interconnection and packaging: impending reality or still a dream?", Digest of Technical Papers, International Solid-State Conference 2004, IEEE-New Jersey, pp.138-145.
2. rd dimension for system integration", Technical Digest of the International Interconnect Technology Conference 2006, IEEE - New Jersey, pp. 1-5.
3. E. Beyne, "System-Driven Approaches to 3D Integration", Proceedings 4th International Symposium on Microelectronics and Packaging, Seoul, South Korea,Sep. 28, 2005.
4. B. Swinnen et al., "3D integration by Cu-Cu thermocompression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias", Technical Digest of the International Electron Device Meeting 2006, pp. 371-374.
5. A. Jourdain, S. Stoukatch, P. De Moor, W. Ruythooren, S. Pargfrieder, B. Swinnen and E. Beyne," Simultaneous Cu-Cu and Compliant Dielectric Bonding for 3D Stacking of ICs", Technical Digest of the International Interconnect Technology Conference 2007, IEEE-New Jersey, pp. 207-209.
6. J. Van Olmen et al., "3D Stacked IC demonstration using a Through Silicon Via First approach", Technical Digest of the International Electron Device Meeting 2007, pp. 603-606.
7. G. Katti et al., "3D Stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective Bonding", unpublished (submitted to IEDM2009 conference).