A novel cache architecture with enhanced performance and security

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue 2008 PROCEEDINGS, 2008, Pages 83-93

  Wang, Zhenghong ^a   Lee, Ruby B ^a  

^a Princeton University   (United States)

Author keywords

Cache; Computer architecture; Performance; Security; Side channel attacks

Indexed keywords

ASSOCIATIVE CACHE; CACHE; CACHE ARCHITECTURE; CACHE INDEX; CACHE MISS; CACHE MISS RATES; CACHE REPLACEMENT ALGORITHM; CIRCUIT DESIGNS; DESIGN GOAL; ENHANCED PERFORMANCE; ENHANCED SOFTWARE; HIGHER-DEGREE; HOT SPOT; INFORMATION LEAKAGE; MISS-RATE; PERFORMANCE; PERFORMANCE DEGRADATION; PERFORMANCE ENHANCING MECHANISMS; POWER EFFICIENCY; POWER EFFICIENT; REMAPPING; SECURITY; SECURITY ISSUES; SECURITY-AWARE; SIDE CHANNEL ATTACK; SIDE CHANNEL ATTACKS;

BUFFER STORAGE; COMPUTER SOFTWARE; COMPUTERS; FAULT TOLERANCE; INTEGRATED CIRCUIT MANUFACTURE; MACHINE DESIGN; QUALITY ASSURANCE;

COMPUTER ARCHITECTURE;

EID: 66749109266     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2008.4771781     Document Type: Conference Paper

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