Enhancing network-on-chip components to support security of processing elements

Proceedings of the 5th Workshop on Embedded Systems Security, WESS '10

Volumn , Issue , 2010, Pages

  Lukovic, Slobodan ^a   Christianos, Nikolaos ^a  

^a UNIVERSITY OF LUGANO   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER OVERFLOWS; DATA ROUTING; FPGA TECHNOLOGY; MULTIPROCESSOR SYSTEM ON CHIPS; NETWORK INTERFACE; NETWORK ON CHIP; PROCESSING ELEMENTS; PROCESSING UNITS; SCALABLE COMMUNICATION; SCALABLE DESIGN; SYSTEM SECURITY;

SERVERS; SYSTEMS ANALYSIS; VLSI CIRCUITS;

EMBEDDED SYSTEMS;

EID: 78650111108     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1873548.1873560     Document Type: Conference Paper

References (26)

1. B. Ahmad, A. Erdogan, and S. Khawam. Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC. In Proceedings of AHS'06, pages 405-411, Jun. 15-18 2006.
2. D. Arora, S. Ravi, A. Raghunathan, and N. K. Jha. Secure embedded processing through hardware-assisted run-time monitoring. In DATE '05: Proceedings of the conference on Design, Automation and Test in Europe, pages 178-183, Washington, DC, USA, 2005. IEEE Computer Society.
3. L. Benini and G. De Micheli. Networks on Chips: A New SoC Paradigm. IEEE Computer, 35(1):70-78, Jan. 2002.
4. T. Benner, R. Ernst, I. Koenenkamp, U. Holtmann, H.-C. Schaub, and N. Serafimov. FPGA Based Prototyping for Verification and Evaluation in Hardware-Software Cosynthesis. In Proceedings of FPL'94, pages 251-258, Sept. 7-9 1994.
5. Bulba and Kil3r. Bypassing StackGuard and StackShield. Phrack Magazine, 10(56), May 2000.
6. C. Ciordas, T. Basten, A. Radulescu, K. Goossens, and J. Van Meerbergen. An Event-Based Monitoring Service for Networks on Chip. ACM Transactions on Design Automation of Electronic Systems, 10(4):702-723, Oct. 2005.
7. C. Ciordas, K. Goossens, T. Basten, A. Radulescu, and A. Boon. Transaction Monitoring in Networks on Chip: The On-Chip Run-Time Perspective. In Proceedings of the Industrial Embedded Systems, 2006. IES '06. International Symposium on, pages 1-10, 2006.
8. C. Cowan, D. Pu, D. Maier, H. Hinton, J. Walpole, P. Bakke, A. Beattie, S. Grier, P. Wagle, and Q. Zhang. Stackguard: Automatic Adaptive Detection and Prevention of Buffer-Overflow Attacks. In Proceedings of the 7th USENIX Security Symposium, 1998.
9. J. W. Dally and T. Brian. Route Packets, Not Wires: On-Chip Inteconnection Networks. In Proceedings of DAC'01, pages 684-689, Jun. 18-22 2001.
10. N. Dor, M. Rodeh, and M. Sagiv. Cssv: towards a realistic tool for statically detecting all buffer overflows in c. In PLDI '03: Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation, pages 155-167, 2003.
11. L. Fiorin, G. Palermo, S. Lukovic, V. Catalano, and C. Silvano. Secure Memory Accesses on Networks-on-Chip. IEEE Trans. on Computers, 57(9):1216-1229, September 2008.
12. L. Fiorin, G. Palermo, S. Lukovic, and C. Silvano. A Data Protection Unit for NoC-based Architectures. In Proceedings of the 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'07), pages 167-172, Sept. 30 - Oct. 5 2007.
13. L. Fiorin, G. Palermo, and C. Silvano. A Security Monitoring Service for NoCs. In Proceedings of the Sixth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'08, pages 197-202, 2008.
14. L. Fiorin, G. Palermo, and C. Silvano. MPSoCs Run-Time Monitoring through Networks-on-Chip. In Proceedings of the Conference on Design, Automation and Test In Europe (DATE'09), pages 558 - 561, Sept. 30 - Oct. 5 2009.
15. M. Frantzen and M. Shuey. Stackghost: Hardware Facilitated Stack Protection. In Proceedings of the 10th USENIX Security Symposium, 2001.
16. R. Hecht, S. Kubisch, A. Herrholtz, and D. Timmermann. Dynamic reconfiguration with hardwired networks-on-chip on future FPGAs. In Proceedings of FPL'05, pages 527-530, Aug. 24-26 2005.
17. I. Hiroaki, J. Sakai, and M. Edahiro. Processor virtualization for secure mobile terminals. ACM Trans. Des. Autom. Electron. Syst., 13(3):1-23, 2008.
18. R. Lee, D. Karig, P. J. Patrick McGregor, and Z. Shi. Enlisting Hardware Architecture to Thwart Malicious Code injection. In SPC, volume 2802 of Lecture Notes in Computer Science, pages 237-252. Springer, 2004.
19. S. Lukovic and L. Fiorin. An Automated Design Flow for NoC-based MPSoCs on FPGA. In Proceedings of 19th IEEE/IFIP International Symposium on Rapid System Prototyping (RSP 2008), 2008.
20. S. Lukovic, P. Pezzino, and L. Fiorin. Stack Protection Unit as a Step Towards Securing MPSoC. In Proceedings of 24nd IEEE International Parallel and Distributed Processing Symposium, 2010.
21. V. Nollet, T. Marescaux, P. Avasare, D. Verkest, and J.-Y. Mignolet. Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware tiles. In Proceedings of DATE'05, pages 234-239, 2005.
22. K. Patel and S. Parameswaran. SHIELD: A Software Hardware Design Methodology for Security and reliability of mpsocs. In DAC '08: Proceedings of the 45th annual conference on Design automation, pages 858-861, New York, NY, USA, 2008.
23. R. Siripokarpirom and F. Mayer-Lindenberg. Hardware-assisted simulation and evaluation of IP cores using FPGA-based rapid prototyping boards. In Proceedings of RSP'04, pages 96-102, Jun. 28-30 2004.
24. D. Wagner and D. Dean. Intrusion detection via static analysis. In SP '01: Proceedings of the 2001 IEEE Symposium on Security and Privacy, 2001.
25. Xilinx. Embedded System Tools Reference Manual.
26. J. Y. Yoon, N. Concer, M. Petracca, and N. Carloni. Virtual Channels vs. Multiple Physical Networks: a Comparative Analysis. In Proceedings of the 47th Design Automation Conference, DAC 2009, San Francisco, CA, USA, June 14-18, 2010. ACM 2010, pages 162-165, 2010.