Efficient timing channel protection for on-chip networks

Proceedings of the 2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012

Volumn , Issue , 2012, Pages 142-151

  Wang, Yao ^a   Suh, G Edward ^a  

^a Cornell University ^*  (United States)

Author keywords

covert channel; on chip network; security; side channel

Indexed keywords

ATTACK VECTOR; CHIP-MULTIPROCESSOR; COVERT CHANNELS; DIRECT COMMUNICATIONS; MULTIPLE FLOWS; ON-CHIP NETWORKS; OTHER APPLICATIONS; PRIORITY-BASED; PROTECTION SCHEMES; SECURITY; SHARED RESOURCES; SIDE CHANNEL ATTACK; SIDE-CHANNEL; STATIC LIMITS; TIMING CHANNELS; TIMING CHARACTERISTICS; TRAFFIC PATTERN;

COMPUTER NETWORKS; INFORMATION SYSTEMS;

EMBEDDED SYSTEMS;

EID: 84862729129     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2012.24     Document Type: Conference Paper

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