-
1
-
-
0036505033
-
The raw microprocessor: A computational fabric for software circuits and general-purpose programs
-
Mar.-Apr.
-
M. B. Taylor, J. Kim, J. Miller, D. Wentzlaff, F. Ghodrat, B. Greenwald, H. Hoffman, P. Johnson, J.-W. Lee, W. Lee, A. Ma, A. Saraf, M. Seneski, N. Shnidman, V. Strumpen, M. Frank, S. Amarasinghe, and A. Agarwal, "The raw microprocessor: A computational fabric for software circuits and general-purpose programs," IEEE Micro, vol. 22, no. 2, pp. 25-35, Mar.-Apr. 2002.
-
(2002)
IEEE Micro
, vol.22
, Issue.2
, pp. 25-35
-
-
Taylor, M.B.1
Kim, J.2
Miller, J.3
Wentzlaff, D.4
Ghodrat, F.5
Greenwald, B.6
Hoffman, H.7
Johnson, P.8
Lee, J.-W.9
Lee, W.10
Ma, A.11
Saraf, A.12
Seneski, M.13
Shnidman, N.14
Strumpen, V.15
Frank, M.16
Amarasinghe, S.17
Agarwal, A.18
-
2
-
-
36849013038
-
On-chip interconnection networks of the TRIPS chip
-
Sep -Oct.
-
P. Gratz, C. Kim, K. Sankaralingam, H. Hanson, P. Shivakumar, S. W. Keckler, and D. Burger, "On-chip interconnection networks of the TRIPS chip," IEEE Micro, vol. 27, no. 5, pp. 41-50, Sep.-Oct. 2007.
-
(2007)
IEEE Micro
, vol.27
, Issue.5
, pp. 41-50
-
-
Gratz, P.1
Kim, C.2
Sankaralingam, K.3
Hanson, H.4
Shivakumar, P.5
Keckler, S.W.6
Burger, D.7
-
3
-
-
36849022584
-
A 5-GHz mesh interconnect for a teraflops processor
-
Sep.-Oct.
-
Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S. Borkar, "A 5-GHz mesh interconnect for a teraflops processor," IEEE Micro, vol. 27, no. 5, pp. 51-61, Sep.-Oct. 2007.
-
(2007)
IEEE Micro
, vol.27
, Issue.5
, pp. 51-61
-
-
Hoskote, Y.1
Vangal, S.2
Singh, A.3
Borkar, N.4
Borkar, S.5
-
4
-
-
36849030305
-
On-chip interconnection architecture of the Tile processor
-
Sep.-Oct.
-
D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards, C. Ramey, M. Mattina, C.-C. Miao, J. F. Brown, III, and A. Agarwal, "On-chip interconnection architecture of the Tile processor," IEEE Micro, vol. 27, no. 5, pp. 15-31, Sep.-Oct. 2007.
-
(2007)
IEEE Micro
, vol.27
, Issue.5
, pp. 15-31
-
-
Wentzlaff, D.1
Griffin, P.2
Hoffmann, H.3
Bao, L.4
Edwards, B.5
Ramey, C.6
Mattina, M.7
Miao, C.-C.8
Brown III, J.F.9
Agarwal, A.10
-
6
-
-
4644301652
-
Low-latency virtual-channel routers for on-chip networks
-
Jun.
-
R. Mullins, A. West, and S. Moore, "Low-latency virtual-channel routers for on-chip networks," in Proc. 31st Annu. Int. Symp. Comput. Arch., Jun. 2004, pp. 1-188.
-
(2004)
Proc. 31st Annu. Int. Symp. Comput. Arch
, pp. 1-188
-
-
Mullins, R.1
West, A.2
Moore, S.3
-
7
-
-
64949183988
-
Prediction router: Yet another low latency on-chip router architecture
-
Feb.
-
H. Matsutani, M. Koibuchi, H. Amano, and T. Yoshinaga, "Prediction router: Yet another low latency on-chip router architecture," in Proc. High-Perform. Comput. Arch., Feb. 2009, pp. 367-378.
-
(2009)
Proc. High-Perform. Comput. Arch
, pp. 367-378
-
-
Matsutani, H.1
Koibuchi, M.2
Amano, H.3
Yoshinaga, T.4
-
8
-
-
66749104350
-
Token flow control
-
Nov.
-
A. Kumar, L.-S. Peh, and N. K. Jha, "Token flow control," in Proc. 41st Int. Symp. Microarch., Nov. 2008, pp. 342-353.
-
(2008)
Proc. 41st Int. Symp. Microarch
, pp. 342-353
-
-
Kumar, A.1
Peh, L.-S.2
Jha, N.K.3
-
9
-
-
35348858651
-
Express virtual channels: Toward the ideal interconnection fabric
-
Jun.
-
A. Kumar, L.-S. Peh, P. Kundu, and N. K. Jha, "Express virtual channels: Toward the ideal interconnection fabric," in Proc. 34th Annu. Int. Symp. Comput. Arch., Jun. 2007, pp. 150-161.
-
(2007)
Proc. 34th Annu. Int. Symp. Comput. Arch
, pp. 150-161
-
-
Kumar, A.1
Peh, L.-S.2
Kundu, P.3
Jha, N.K.4
-
10
-
-
77955985774
-
A low-latency NoC router with lookahead bypass
-
Jun.
-
L. Xin and C. S. Choy, "A low-latency NoC router with lookahead bypass," in Proc. Int. Symp. Circuits Syst., Jun. 2010, pp. 3981-3984.
-
(2010)
Proc. Int. Symp. Circuits Syst
, pp. 3981-3984
-
-
Xin, L.1
Choy, C.S.2
-
11
-
-
52949114554
-
A 4.6 Tbits/s 3.6 GHz single-cycle NoC router with a novel switch allocator in 65 nm CMOS
-
Oct.
-
A. Kumar, P. Kunduz, A. P. Singhx, L.-S. Pehy, and N. K. Jhay, "A 4.6 Tbits/s 3.6 GHz single-cycle NoC router with a novel switch allocator in 65 nm CMOS," in Proc. 25th Int. Conf. Comput. Design, Oct. 2007, pp. 63-70.
-
(2007)
Proc. 25th Int. Conf. Comput. Design
, pp. 63-70
-
-
Kumar, A.1
Kunduz, P.2
Singhx, A.P.3
Pehy, L.-S.4
Jhay, N.K.5
-
12
-
-
51749116188
-
A 0.6 pJ/b 3 Gb/s/ch transceiver in 0.18 μm CMOS for 10 mm on-chip interconnects
-
May
-
J. Bae, J.-Y. Kim, and H.-J. Yoo, "A 0.6 pJ/b 3 Gb/s/ch transceiver in 0.18 μm CMOS for 10 mm on-chip interconnects," in Proc. IEEE Int. Symp. Circuit Syst., May 2008, pp. 2861-2864.
-
(2008)
Proc. IEEE Int. Symp. Circuit Syst
, pp. 2861-2864
-
-
Bae, J.1
Kim, J.-Y.2
Yoo, H.-J.3
-
13
-
-
70349292818
-
A 4Gb/s/ch 356 fJ/b 10 mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90 nm CMOS
-
Feb.
-
B. Kim and V. Stojanovic, "A 4Gb/s/ch 356 fJ/b 10 mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90 nm CMOS," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2009, pp. 66-68.
-
(2009)
Proc. IEEE Int. Solid-State Circuits Conf
, pp. 66-68
-
-
Kim, B.1
Stojanovic, V.2
-
14
-
-
31344479337
-
A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects
-
Jan.
-
D. Schinkel, E. Mensink, E. A. M. Klumperink, E. van Tuijl, and B. Nauta, "A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 297-306, Jan. 2006.
-
(2006)
IEEE J. Solid-State Circuits
, vol.41
, Issue.1
, pp. 297-306
-
-
Schinkel, D.1
Mensink, E.2
Klumperink, E.A.M.3
Van Tuijl, E.4
Nauta, B.5
-
15
-
-
33645011974
-
Low-power network-on-chip for highperformance SoC design
-
Feb.
-
K. Lee, S.-J. Lee, and H.-J. Yoo, "Low-power network-on-chip for highperformance SoC design," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 2, pp. 148-160, Feb. 2006.
-
(2006)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
, vol.14
, Issue.2
, pp. 148-160
-
-
Lee, K.1
Lee, S.-J.2
Yoo, H.-J.3
-
16
-
-
84862144932
-
Power-driven design of router microarchitectures in on-chip networks
-
H.-S. Wang, L.-S. Peh, and S. Malik, "Power-driven design of router microarchitectures in on-chip networks," in Proc. 36th Annu. IEEE/ACM Int. Symp., Dec. 2003, pp. 105-116.
-
(2003)
Proc. 36th Annu. IEEE/ACM Int. Symp., Dec.
, pp. 105-116
-
-
Wang, H.-S.1
Peh, L.-S.2
Malik, S.3
-
17
-
-
84955452760
-
Dynamic voltage scaling with links for power optimization of interconnection networks
-
Feb.
-
L. Shang, L.-S. Peh, and N. Jha, "Dynamic voltage scaling with links for power optimization of interconnection networks," in Proc. High-Perform. Comput. Arch., Feb. 2003, pp. 91-102.
-
(2003)
Proc. High-Perform. Comput. Arch
, pp. 91-102
-
-
Shang, L.1
Peh, L.-S.2
Jha, N.3
-
18
-
-
84862964953
-
A low-swing crossbar and link generator for low-power networks-on-chip
-
Nov.
-
C.-H. Chen, S. Park, T. Krishna, and L.-S. Peh, "A low-swing crossbar and link generator for low-power networks-on-chip," in Proc. Int. Conf. Comput.-Aided Design, Nov. 2011, pp. 779-786.
-
(2011)
Proc. Int. Conf. Comput.-Aided Design
, pp. 779-786
-
-
Chen, C.-H.1
Park, S.2
Krishna, T.3
Peh, L.-S.4
-
19
-
-
67649642145
-
Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs)
-
Mar.
-
A. Kodi, A. Louri, and J. Wang, "Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs)," in Proc. Int. Symp. Qual. Electron. Design, Mar. 2009, pp. 826-832.
-
(2009)
Proc. Int. Symp. Qual. Electron. Design
, pp. 826-832
-
-
Kodi, A.1
Louri, A.2
Wang, J.3
-
20
-
-
47349129525
-
Flattened butterfly topology for on-chip networks
-
Chicago, IL, Dec.
-
J. Kim, J. Balfour, and W. Dally, "Flattened butterfly topology for on-chip networks," in Proc. 40th Annu. IEEE/ACM Int. Symp. Micro, Chicago, IL, Dec. 2007, pp. 172-182.
-
(2007)
Proc. 40th Annu. IEEE/ACM Int. Symp. Micro
, pp. 172-182
-
-
Kim, J.1
Balfour, J.2
Dally, W.3
-
21
-
-
64949139014
-
Elastic-buffer flow control for on-chip networks
-
Feb.
-
G. Michelogiannakis, J. Balfour, and W. Dally, "Elastic-buffer flow control for on-chip networks," in Proc. High-Perform. Comput. Arch., Feb. 2009, pp. 151-162.
-
(2009)
Proc. High-Perform. Comput. Arch
, pp. 151-162
-
-
Michelogiannakis, G.1
Balfour, J.2
Dally, W.3
-
22
-
-
84881110775
-
Scalable pipelined interconnect for distributed endpoint routing: The SGI SPIDER chip
-
Aug.
-
M. Galles, "Scalable pipelined interconnect for distributed endpoint routing: The SGI SPIDER chip," in Proc. High-Perform. Interconn., Aug. 1996, pp. 1-6.
-
(1996)
Proc. High-Perform. Interconn
, pp. 1-6
-
-
Galles, M.1
-
23
-
-
80052543351
-
TLSync: Support for multiple fast barriers using on-chip transmission lines
-
J. Oh, M. Prvulovic, and A. Zajic, "TLSync: Support for multiple fast barriers using on-chip transmission lines," in Proc. 38th Annu. Int. Symp. Comput. Arch., 2011, pp. 105-116.
-
(2011)
Proc. 38th Annu. Int. Symp. Comput. Arch.
, pp. 105-116
-
-
Oh, J.1
Prvulovic, M.2
Zajic, A.3
-
24
-
-
57849125522
-
NoC with near-ideal express virtual channels using global-line communication
-
T. Krishna A. Kumar, P. Chiang, M. Erez, and L.-S. Peh, "NoC with near-ideal express virtual channels using global-line communication," in Proc. High-Perform. Interconn., 2008, pp. 11-20.
-
(2008)
Proc. High-Perform. Interconn.
, pp. 11-20
-
-
Krishna, T.1
Kumar, A.2
Chiang, P.3
Erez, M.4
Peh, L.-S.5
-
25
-
-
58849136152
-
Low-power, high-speed transceivers for network-on-chip communication
-
Jan.
-
D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B. Nauta, "Low-power, high-speed transceivers for network-on-chip communication," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 1, pp. 12-21, Jan. 2009.
-
(2009)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
, vol.17
, Issue.1
, pp. 12-21
-
-
Schinkel, D.1
Mensink, E.2
Klumperink, E.3
Van Tuijl, E.4
Nauta, B.5
-
26
-
-
73249146452
-
A 45 nm 8-core enterprise Xeon® processor
-
Jan.
-
S. Rusu, S. Tam, H. Muljono, D. Ayers, J. Chang, R. Varada, M. Ratta, and S. Vora, "A 45 nm 8-core enterprise Xeon® processor," IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 7-14, Jan. 2010.
-
(2010)
IEEE J. Solid-State Circuits
, vol.45
, Issue.1
, pp. 7-14
-
-
Rusu, S.1
Tam, S.2
Muljono, H.3
Ayers, D.4
Chang, J.5
Varada, R.6
Ratta, M.7
Vora, S.8
-
27
-
-
33749169344
-
Optimally-placed twists in global on-chip differential interconnects
-
Sep.
-
E. Mensink, D. Schinkel, E. Klumperink, E. van Tuijl, and B. Nauta, "Optimally-placed twists in global on-chip differential interconnects," in Proc. Eur. Solid-State Circuits Conf., Sep. 2005, pp. 475-478.
-
(2005)
Proc. Eur. Solid-State Circuits Conf
, pp. 475-478
-
-
Mensink, E.1
Schinkel, D.2
Klumperink, E.3
Van Tuijl, E.4
Nauta, B.5
-
28
-
-
0034818435
-
A delay model and speculative architecture for pipelined routers
-
Jan.
-
L.-S. Peh and W. J. Dally, "A delay model and speculative architecture for pipelined routers," in Proc. High-Perform. Comput. Arch., Jan. 2001, pp. 255-266.
-
(2001)
Proc. High-Perform. Comput. Arch
, pp. 255-266
-
-
Peh, L.-S.1
Dally, W.J.2
-
29
-
-
80455168140
-
Energy-efficient transceiver circuits for short-range on-chip interconnects
-
Sep.
-
J. Postman and P. Chiang, "Energy-efficient transceiver circuits for short-range on-chip interconnects," in Proc. Custom Integr. Circuits Conf., Sep. 2011, pp. 1-4.
-
(2011)
Proc. Custom Integr. Circuits Conf
, pp. 1-4
-
-
Postman, J.1
Chiang, P.2
|