A 4Gb/s/ch 356fJ/b 10mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages

  Kim, Byungsub ^a   Stojanovic, Vladimir ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349292818     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977310     Document Type: Conference Paper

References (8)

1. E. Mensink, D. Schinkel, E. Klumperinck, et al., "A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-chip interconnects," ISSCC Dig. Tech. Papers, pp. 314-315, Dec. 2007.
2. R. Ho, I. Ono, F. Liu, et al., "High-Speed and Low-Energy Capacitive-Driven On-Chip Wires," ISSCC Dig. Tech. Papers, pp. 412-413, Dec. 2007.
3. B. Kim and V. Stojanovi "Equalized Interconnect for On-Chip Networks: Modeling and Optimization Framework," ICCAD, pp. 552-559, Nov. 2007.
4. L. Zhang, J. Wilson, R. Bashirullah, et al, "A 32Gb/s On-chip Bus with Driver Preemphasis Signaling," CICC, pp. 265-268, Sep. 2006.
5. J.F. Bulzacchelli, M. Meghelli, S.V. Rylov, et al., "A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology," J. Solid-State Circuits, vol.41, no.12, pp. 2885-2900, Dec. 2006.
6. R. Bashirullah, W. Lieu, R. Cavi, D. Edwards, "A 16Gb/s Adaptive Bandwidth On-chip Bus based on Hybrid Current/voltage Mode Signaling," Symp. VLSI Circuits, pp. 392- 393, Jun. 2004.
7. N. Tzartzanis, W.W. Walker, "Differential Current-Mode Sensing for Efficient On-Chip Global Signaling," J. Solid-State Circuits, vol.40, no.11, pp. 2141-2147, Nov. 2005.
8. V. Stojanovic, A. Ho, B. Garlepp, et al. "Adaptive Equalization and Data Recovery in Dual-Mode (PAM2/4) Serial Link Tranceiver," Symp. VLSI Circuits, pp. 348-351, Jun. 2004.