A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 1, 2006, Pages 297-306

  Schinkel, D ^a   Mensink, E ^a   Klumperink, E A M ^a   Van Tuijl, E ^a   Nauta, B ^a  

^a UNIVERSITY OF TWENTE   (Netherlands)

Author keywords

Bus transceiver; Crosstalk mitigation; Differential interconnects; Equalization techniques; Layout technique; On chip interconnects; RC limited interconnects; Repeater insertion approach; Termination technique; Transceiver; Uninterrupted interconnect

Indexed keywords

CMOS INTEGRATED CIRCUITS; CROSSTALK; DIFFERENTIATING CIRCUITS; EQUALIZERS; INTEGRATED CIRCUIT LAYOUT; TELECOMMUNICATION REPEATERS; TRANSCEIVERS; TRANSISTORS;

BUS-TRANSCEIVER; CROSSTALK MITIGATION; DIFFERENTIAL INTERCONNECTS; EQUALIZATION TECHNIQUES; LAYOUT TECHNIQUE; ON-CHIP INTERCONNECTS; RC-LIMITED INTERCONNECTS; REPEATER INSERTION APPROACH; TERMINATION TECHNIQUE; UNINTERRUPTED INTERCONNECT;

DATA COMMUNICATION EQUIPMENT;

EID: 31344479337     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.859880     Document Type: Article

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