Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs)

Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009

Volumn , Issue , 2009, Pages 826-832

  Kodi, Avinash ^a   Louri, Ahmed ^b   Wang, Janet ^b  

^a US Institute of Navigation   (United States)

^b University of Arizona   (United States)

Author keywords

Channel Buffers; Network on Chips (NoCs); Router Bypassing

Indexed keywords

ADAPTIVE CHANNEL BUFFERS; ATTRACTIVE SOLUTIONS; CHANNEL BUFFERS; ENERGY EFFICIENT; IN-CHIP; INTERCONNECT DELAY; NETWORK-ON-CHIP ARCHITECTURES; NETWORK-ON-CHIPS; NETWORK-ON-CHIPS (NOCS); PERFORMANCE IMPROVEMENTS; POWER CONSUMPTION; POWER DISSIPATION; POWER REDUCTIONS; ROUTER BUFFER; ROUTER PIPELINE; SIMULATION RESULT;

BIOLOGICAL MATERIALS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER UTILIZATION; ENERGY EFFICIENCY; MICROPROCESSOR CHIPS; PIPELINES; WIRE;

ROUTERS;

EID: 67649642145     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2009.4810399     Document Type: Conference Paper

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