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Volumn , Issue , 2011, Pages 779-786

A low-swing crossbar and link generator for low-power networks-on-chip

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATED LAYOUT; CUSTOM CIRCUITS; DATA PATHS; HIGH BIT RATES; IN-CHIP; IP BLOCK; LOW POWER; LOW SWING; MULTI-PROCESSORS; NETWORKS ON CHIPS; POWER EFFICIENCY; POWER REDUCTIONS; SYSTEMS ON CHIPS;

EID: 84862964953     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2011.6105418     Document Type: Conference Paper
Times cited : (18)

References (23)
  • 3
    • 36849030305 scopus 로고    scopus 로고
    • On-chip interconnection architecture of the tile processor
    • D. Wentzlaff et al., "On-chip interconnection architecture of the tile processor," IEEE Micro, vol. 27, no. 5, pp. 15-31, 2007.
    • (2007) IEEE Micro , vol.27 , Issue.5 , pp. 15-31
    • Wentzlaff, D.1
  • 4
    • 36849022584 scopus 로고    scopus 로고
    • A 5-ghz mesh interconnect for a teraflops processor
    • September
    • Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S. Borkar, "A 5-ghz mesh interconnect for a teraflops processor," IEEE Micro, vol. 27, no. 5, pp. 51-61, September 2007.
    • (2007) IEEE Micro , vol.27 , Issue.5 , pp. 51-61
    • Hoskote, Y.1    Vangal, S.2    Singh, A.3    Borkar, N.4    Borkar, S.5
  • 7
    • 33745160052 scopus 로고    scopus 로고
    • A six-port 57gb/s doublepumped nonblocking router core
    • June
    • S. Vangal, N. Borkar, and A. Alvandpour, "A six-port 57gb/s doublepumped nonblocking router core," in Symp. VLSI Circuits, June 2005, pp. 268-269.
    • (2005) Symp. VLSI Circuits , pp. 268-269
    • Vangal, S.1    Borkar, N.2    Alvandpour, A.3
  • 10
    • 70349292818 scopus 로고    scopus 로고
    • A 4gb/s/ch 356fj/b 10mm equalized onchip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90nm cmos
    • Feb.
    • B. Kim and V. Stojanovic, "A 4gb/s/ch 356fj/b 10mm equalized onchip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90nm cmos," IEEE International Solid-State Circuits Conference, Digest of Technical Papers., pp. 66-68, Feb. 2009.
    • (2009) IEEE International Solid-State Circuits Conference, Digest of Technical Papers. , pp. 66-68
    • Kim, B.1    Stojanovic, V.2
  • 15
    • 57849123638 scopus 로고    scopus 로고
    • Optimization-based framework for simultaneous circuit-and-system design-space exploration: A high-speed link example
    • R. Sredojevic and V. Stojanovic, "Optimization-based framework for simultaneous circuit-and-system design-space exploration: A high-speed link example," Computer-Aided Design, International Conference on, vol. 0, pp. 314-321, 2008.
    • (2008) Computer-Aided Design, International Conference on , pp. 314-321
    • Sredojevic, R.1    Stojanovic, V.2
  • 16
    • 84862914834 scopus 로고    scopus 로고
    • "ARM AMBA," http://www.arm.com/products/system-ip/amba.
  • 19
    • 84862912594 scopus 로고    scopus 로고
    • "IBM CoreConnect," https://www-01.ibm.com/chips/techlib/ techlib.nsf/productfamilies/CoreConnectBusArchitecture.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.