A 45 nm 8-Core enterprise xeon® processor

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 1, 2010, Pages 7-14

  Rusu, Stefan ^a   Tam, Simon ^a   Muljono, Harry ^a   Stinson, Jason ^a   Ayers, David ^a   Chang, Jonathan ^a   Varada, Raj ^a   Ratta, Matt ^a   Kottapalli, Sailesh ^a   Vora, Sujal ^a  

^a INTEL CORPORATION   (United States)

Author keywords

45 nmprocess technology; Circuit design; Clock distribution; Computer architecture; Core recovery; Leakage reduction; Microprocessor; Voltage domains

Indexed keywords

CIRCUIT DESIGNS; CLOCK DISTRIBUTION; LEAKAGE REDUCTION; MICROPROCESSOR; VOLTAGE DOMAINS;

COMPUTERS; CONVERSION EFFICIENCY; ELECTRIC CLOCKS; ELECTRIC POTENTIAL; INTEGRATED CIRCUIT MANUFACTURE; METAL RECOVERY; MICROPROCESSOR CHIPS; VOLTAGE REGULATORS;

COMPUTER ARCHITECTURE;

EID: 73249146452     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2034076     Document Type: Conference Paper

References (7)

1. K. Mistry et al., "A 45 nm logic technology with high-k metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging," in IEDM Tech. Dig., Dec. 2007.
2. R. Kumar and G. Hinton, "A family of 45 nm IA processors," in IEEE ISSCC Dig. Tech. Papers, Feb. 2009.
3. J. Chang et al., "A 45 nm 24 MB on-die L3 cache for the 8-core multithreaded Xeon® processor," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2009.
4. F. Hamzaoglu et al., "A 153 Mb-SRAM design with dynamic stability enhancement and leakage reduction in 45 nm high-K metal-gateCMOS technology," in IEEE ISSCC Dig. Tech. Papers, Feb. 2008.
5. S. Tam et al., "Clock generation and distribution for a 45 nm, 8-core Xeon® processor with 24 MB," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2009.
6. R. Varada et al., "Design and integration methods for a multi-threaded dual core 65 nm Xeon® processor," in Proc. Int. Conf. Computer-Aided Design (ICCAD), 2006.
7. R. Varada et al., "Automated pseudo-flat design methodology for register array design," in Proc. Design Automation Conf., 2009.