-
1
-
-
79957524588
-
Dynamic connectivity: Connecting to networks and geometry
-
T. M. Chan, M. Patraşcu, and L. Roditty, "Dynamic connectivity: Connecting to networks and geometry," SIAM J. Comput., vol. 40, no. 2, pp. 333-349, 2011.
-
(2011)
SIAM J. Comput.
, vol.40
, Issue.2
, pp. 333-349
-
-
Chan, T.M.1
Patraşcu, M.2
Roditty, L.3
-
2
-
-
84861640909
-
An optimal dynamic data structure for stabbing-semigroup queries
-
P. K. Agarwal, L. Arge, H. Kaplan, E. Molad, R. E. Tarjan, and K. Yi, "An optimal dynamic data structure for stabbing-semigroup queries," SIAM J. Comput., vol. 41, no. 1, pp. 104-127, 2012.
-
(2012)
SIAM J. Comput.
, vol.41
, Issue.1
, pp. 104-127
-
-
Agarwal, P.K.1
Arge, L.2
Kaplan, H.3
Molad, E.4
Tarjan, R.E.5
Yi, K.6
-
3
-
-
0344236266
-
Metaheuristics in combinatorial optimization: Overview and conceptual comparison
-
C. Blum and A. Roli, "Metaheuristics in combinatorial optimization: Overview and conceptual comparison," ACM Computing Surveys, vol. 35, no. 3, pp. 268-308, 2003.
-
(2003)
ACM Computing Surveys
, vol.35
, Issue.3
, pp. 268-308
-
-
Blum, C.1
Roli, A.2
-
4
-
-
33748097477
-
Fast floorplanning by look-ahead enabled recursive bipartitioning
-
DOI 10.1109/TCAD.2005.859519, 1673746
-
J. Cong, M. Romesis, and J. R. Shinnerl, "Fast floorplanning by lookahead enabled recursive bipartitioning," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 25, no. 9, pp. 1719-1732, Sep. 2006. (Pubitemid 44304101)
-
(2006)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.25
, Issue.9
, pp. 1719-1732
-
-
Cong, J.1
Romesis, M.2
Shinnerl, J.R.3
-
5
-
-
57849111334
-
A novel fixedoutline floorplanner with zero deadspace for hierarchical design
-
O. He, S. Dong, J. Bian, S. Goto, and C.-K. Cheng, "A novel fixedoutline floorplanner with zero deadspace for hierarchical design," in Proc. Int. Conf. Comput.-Aided Design, 2008, pp. 16-23.
-
(2008)
Proc. Int. Conf. Comput.-Aided Design
, pp. 16-23
-
-
He, O.1
Dong, S.2
Bian, J.3
Goto, S.4
Cheng, C.-K.5
-
6
-
-
77649159236
-
DeFer: Deferred decision making enabled fixed-outline floorplanning algorithm
-
Mar.
-
J. Z. Yan and C. Chu, "DeFer: Deferred decision making enabled fixed-outline floorplanning algorithm," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 29, no. 3, pp. 367-381, Mar. 2010.
-
(2010)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.
, vol.29
, Issue.3
, pp. 367-381
-
-
Yan, J.Z.1
Chu, C.2
-
7
-
-
84954416950
-
Multi-level placement for largescale mixed-size IC designs
-
C.-C. Chang, J. Cong, and X. Yuan, "Multi-level placement for largescale mixed-size IC designs," in Proc. 2003 Asia South Pacific Design Autom. Conf., 2003, pp. 325-330.
-
(2003)
Proc. 2003 Asia South Pacific Design Autom. Conf.
, pp. 325-330
-
-
Chang, C.-C.1
Cong, J.2
Yuan, X.3
-
8
-
-
70350714592
-
Handling complexities in modern large-scale mixed-size placement
-
J. Z. Yan, N. Viswanathan, and C. Chu, "Handling complexities in modern large-scale mixed-size placement," in Proc. 46th Annu. Design Autom. Conf., 2009, pp. 436-441.
-
(2009)
Proc. 46th Annu. Design Autom. Conf.
, pp. 436-441
-
-
Yan, J.Z.1
Viswanathan, N.2
Chu, C.3
-
9
-
-
84255204462
-
SimPL: An effective placement algorithm
-
Jan.
-
M.-C. Kim, D.-J. Lee, and I. L. Markov, "SimPL: An effective placement algorithm," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 31, no. 1, pp. 50-60, Jan. 2012.
-
(2012)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.
, vol.31
, Issue.1
, pp. 50-60
-
-
Kim, M.-C.1
Lee, D.-J.2
Markov, I.L.3
-
10
-
-
33645694781
-
Modern floorplanning based on B-tree and fast simulated annealing
-
Apr.
-
T.-C. Chen and Y.-W. Chang, "Modern floorplanning based on B-tree and fast simulated annealing," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 25, no. 4, pp. 637-650, Apr. 2006.
-
(2006)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.
, vol.25
, Issue.4
, pp. 637-650
-
-
Chen, T.-C.1
Chang, Y.-W.2
-
11
-
-
79959207947
-
UFO: Unified convex optimization algorithms for fixed-outline floorplanning considering pre-placed modules
-
Jul.
-
J.-M. Lin and Z.-X. Hung, "UFO: Unified convex optimization algorithms for fixed-outline floorplanning considering pre-placed modules," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 30, no. 7, pp. 1034-1044, Jul. 2011.
-
(2011)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.
, vol.30
, Issue.7
, pp. 1034-1044
-
-
Lin, J.-M.1
Hung, Z.-X.2
-
12
-
-
16244382367
-
Unification of partitioning, placement and floorplanning
-
7C.1, ICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
-
S. N. Adya, S. Chaturvedi, J. A. Roy, D. A. Papa, and I. L. Markov, "Unification of partitioning, placement and floorplanning," in Proc. 2004 IEEE/ACM Int. Conf. Comput.-Aided Des., 2004, pp. 550-557. (Pubitemid 40449287)
-
(2004)
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
, pp. 550-557
-
-
Adya, S.N.1
Chaturvedi, S.2
Roy, J.A.3
Papa, D.A.4
Markov, I.L.5
-
13
-
-
0033704928
-
An enhanced perturbing algorithm for floorplan design using the O-tree representation
-
Y. Pang, C.-K. Cheng, and T. Yoshimura, "An enhanced perturbing algorithm for floorplan design using the O-tree representation," in Proc. 2000 Int. Symp. Phys. Des., 2000, pp. 168-73.
-
(2000)
Proc. 2000 Int. Symp. Phys. Des.
, pp. 168-173
-
-
Pang, Y.1
Cheng, C.-K.2
Yoshimura, T.3
-
14
-
-
0034855935
-
TCG: A transitive closure graph-based representation for non-slicing floorplans
-
J.-M. Lin and Y.-W. Chang, "TCG: A transitive closure graph-based representation for non-slicing floorplans," in Proc. 38th Annu. Des. Autom. Conf., 2001, pp. 764-769. (Pubitemid 32841052)
-
(2001)
Proceedings - Design Automation Conference
, pp. 764-769
-
-
Lin, J.-M.1
Chang, Y.-W.2
-
15
-
-
77956060554
-
New perspectives in VLSI design automation: Deterministic packing by sequence pair
-
A. Janiak, A. Kozik, and M. Lichtenstein, "New perspectives in VLSI design automation: Deterministic packing by sequence pair," Ann. Oper. Res., vol. 179, no. 1, pp. 35-56, 2010.
-
(2010)
Ann. Oper. Res.
, vol.179
, Issue.1
, pp. 35-56
-
-
Janiak, A.1
Kozik, A.2
Lichtenstein, M.3
-
16
-
-
3142780559
-
Placement constraints in floorplan design
-
Jul.
-
E. F. Y. Young, C. C. N. Chu, and M. L. Ho, "Placement constraints in floorplan design," IEEE Trans. Very Large Scale Integr. Syst., vol. 12, no. 7, pp. 735-745, Jul. 2004.
-
(2004)
IEEE Trans. Very Large Scale Integr. Syst.
, vol.12
, Issue.7
, pp. 735-745
-
-
Young, E.F.Y.1
Chu, C.C.N.2
Ho, M.L.3
-
17
-
-
53849137014
-
Constraintdriven floorplan repair
-
M. D. Moffitt, J. A. Roy, I. L. Markov, and M. E. Pollack, "Constraintdriven floorplan repair," ACM Trans. Des. Autom. Electron. Syst., vol. 13, no. 4, pp. 1-13, 2008.
-
(2008)
ACM Trans. Des. Autom. Electron. Syst.
, vol.13
, Issue.4
, pp. 1-13
-
-
Moffitt, M.D.1
Roy, J.A.2
Markov, I.L.3
Pollack, M.E.4
-
18
-
-
84856433796
-
Assembling 2-D blocks into 3-D chips
-
Feb.
-
J. Knechtel, I. L. Markov, and J. Lienig, "Assembling 2-D blocks into 3-D chips," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 31, no. 2, pp. 228-241, Feb. 2012.
-
(2012)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.
, vol.31
, Issue.2
, pp. 228-241
-
-
Knechtel, J.1
Markov, I.L.2
Lienig, J.3
-
19
-
-
0030378255
-
VLSI module placement based on rectangle-packing by the sequence-pair
-
PII S0278007096094134
-
H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "VLSI module placement based on rectangle-packing by the sequence pair," IEEE Trans. CAD ICs., vol. 15, no. 12, pp. 1518-1524, Dec. 1996. (Pubitemid 126780413)
-
(1996)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.15
, Issue.12
, pp. 1518-1524
-
-
Murata, H.1
Fujiyoshi, K.2
Nakatake, S.3
Kajitani, Y.4
-
20
-
-
0029488327
-
Rectanglepacking based module placement
-
H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "Rectanglepacking based module placement," in Proc. ICCAD, 1995, pp. 472-479.
-
(1995)
Proc. ICCAD
, pp. 472-479
-
-
Murata, H.1
Fujiyoshi, K.2
Nakatake, S.3
Kajitani, Y.4
-
22
-
-
0003962144
-
An algorithm for finding a maximum-weight decreasing sequence in a permutation, motivated by rectangle packing problem
-
T. Takahashi, "An algorithm for finding a maximum-weight decreasing sequence in a permutation, motivated by rectangle packing problem," IEICE Tech. Rep. VLSI Design Technol., vol. VLD96. no. 7, pp. 31-35, 1996.
-
(1996)
IEICE Tech. Rep. VLSI Design Technol.
, vol.VLD96.
, Issue.7
, pp. 31-35
-
-
Takahashi, T.1
-
23
-
-
0035670932
-
Fast evaluation of sequence pair in block placement by longest common subsequence computation
-
DOI 10.1109/43.969434, PII S027800700110641X
-
X. Tang, R. Tian, and D. Wong, "Fast evaluation of sequence pair in block placement by longest common subsequence computation," IEEE Trans. CAD ICs., vol. 20, no. 12, pp. 1406-1413, Dec. 2001. (Pubitemid 34035689)
-
(2001)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.20
, Issue.12
, pp. 1406-1413
-
-
Tang, X.1
Tian, R.2
Wong, D.F.3
-
24
-
-
0017492836
-
A fast algorithm for computing longest common subsequences
-
J. Hunt and T. Szymanski, "A fast algorithm for computing longest common subsequences," Commun. ACM, vol. 20, no. 5, pp. 350-353, 1977.
-
(1977)
Commun. ACM
, vol.20
, Issue.5
, pp. 350-353
-
-
Hunt, J.1
Szymanski, T.2
-
25
-
-
0037218783
-
Floorplan representations: Complexity and connections
-
DOI 10.1145/606603.606607
-
B. Yao, H. Chen, C.-K. Cheng, and R. Graham, "Floorplan representations: Complexity and connections," ACM Trans. Des. Autom. Electron. Syst., vol. 8, no. 1, pp. 55-80, 2003. (Pubitemid 36320984)
-
(2003)
ACM Transactions on Design Automation of Electronic Systems
, vol.8
, Issue.1
, pp. 55-80
-
-
Yao, B.1
Chen, H.2
Cheng, C.-K.3
Graham, R.4
-
26
-
-
50549094673
-
MP-trees: A packing-based macro placement algorithm for mixed-size designs
-
Sep.
-
T.-C. Chen, P.-H. Yuh, Y.-W. Chang, F.-J. Huang, and D. Liu, "MP-trees: A packing-based macro placement algorithm for mixed-size designs," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 27, no. 9, pp. 1621-1634, Sep. 2008.
-
(2008)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.
, vol.27
, Issue.9
, pp. 1621-1634
-
-
Chen, T.-C.1
Yuh, P.-H.2
Chang, Y.-W.3
Huang, F.-J.4
Liu, D.5
-
27
-
-
0141750617
-
Corner sequence: A P-admissible floorplan representation with a worst case linear-time packing scheme
-
Aug.
-
J.-M. Lin, Y.-W. Chang, and S.-P. Lin, "Corner sequence: A P-admissible floorplan representation with a worst case linear-time packing scheme," IEEE Trans. Very Large Scale Integr. Syst., vol. 11, no. 4, pp. 679-686, Aug. 2003.
-
(2003)
IEEE Trans. Very Large Scale Integr. Syst.
, vol.11
, Issue.4
, pp. 679-686
-
-
Lin, J.-M.1
Chang, Y.-W.2
Lin, S.-P.3
-
28
-
-
0032690067
-
An O-tree representation of non-slicing floorplan and its applications
-
Jun.
-
P.-N. Guo, C.-K. Cheng, and T. Yoshimura, "An O-tree representation of non-slicing floorplan and its applications," in Proc. 36th Annu. ACM/IEEE Design Automation Conf., Jun. 1999, pp. 268-273.
-
(1999)
Proc. 36th Annu. ACM/IEEE Design Automation Conf.
, pp. 268-273
-
-
Guo, P.-N.1
Cheng, C.-K.2
Yoshimura, T.3
-
29
-
-
0033701594
-
B-trees: A new representation for non-slicing floorplans
-
Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu, "B-trees: A new representation for non-slicing floorplans," in Proc. 37th Annu. Des. Autom. Conf., 2000, pp. 458-463.
-
(2000)
Proc. 37th Annu. Des. Autom. Conf.
, pp. 458-463
-
-
Chang, Y.-C.1
Chang, Y.-W.2
Wu, G.-M.3
Wu, S.-W.4
-
30
-
-
84856447968
-
Optimal slack-driven block shaping algorithm in fixed-outline floorplanning
-
J. Z. Yan and C. Chu, "Optimal slack-driven block shaping algorithm in fixed-outline floorplanning," in Proc. 2012 ACM Int. Symp. Phys. Des., 2012, pp. 179-186.
-
(2012)
Proc. 2012 ACM Int. Symp. Phys. Des.
, pp. 179-186
-
-
Yan, J.Z.1
Chu, C.2
-
31
-
-
4344684112
-
Selected Sequence-Pair: An efficient decodable packing representation in linear time using sequence-pair
-
C. Kodama and K. Fujiyoshi, "Selected Sequence-Pair: An efficient decodable packing representation in linear time using sequence-pair," in Proc. DAC, pp. 331-337, 2003.
-
(2003)
Proc. DAC
, pp. 331-337
-
-
Kodama, C.1
Fujiyoshi, K.2
-
32
-
-
84949810913
-
Module placement with boundary constraints using the sequence-pair representation
-
J. Lai, M.-S. Lin, T.-C. Wang, and L.-C. Wang, "Module placement with boundary constraints using the sequence-pair representation," in Proc. 2001 Asia South Pacific Des. Autom. Conf., 2001, pp. 515-520.
-
(2001)
Proc. 2001 Asia South Pacific Des. Autom. Conf.
, pp. 515-520
-
-
Lai, J.1
Lin, M.-S.2
Wang, T.-C.3
Wang, L.-C.4
-
33
-
-
84945709402
-
An improved equivalence algorithm
-
B. Galler and M. Fischer, "An improved equivalence algorithm," Comm. ACM, vol. 7, no. 5, pp. 301-303, 1964.
-
(1964)
Comm. ACM
, vol.7
, Issue.5
, pp. 301-303
-
-
Galler, B.1
Fischer, M.2
-
35
-
-
34250391491
-
Design and implementation of an efficient priority queue
-
P. van Emde Boas, R. Kaas, and E. Zijlstra, "Design and implementation of an efficient priority queue," Math. Syst. Theory, vol. 10, no. 1, pp. 99-127, 1977.
-
(1977)
Math. Syst. Theory
, vol.10
, Issue.1
, pp. 99-127
-
-
Boas Emde P.Van1
Kaas, R.2
Zijlstra, E.3
-
36
-
-
34250239747
-
A priority queue in which initialization and queue operations take O(log logD) time
-
D. Johnson, "A priority queue in which initialization and queue operations take O(log logD) time," Math. Syst. Theory, vol. 15, no. 4, pp. 295-309, 1982.
-
(1982)
Math. Syst. Theory
, vol.15
, Issue.4
, pp. 295-309
-
-
Johnson, D.1
-
37
-
-
0024860011
-
The cell probe complexity of dynamic data structures
-
M. Fredman and M. Saks, "The cell probe complexity of dynamic data structures," in Proc. STOC, pp. 345-354, 1989.
-
(1989)
Proc. STOC
, pp. 345-354
-
-
Fredman, M.1
Saks, M.2
-
38
-
-
65549083420
-
Worst case constant time priority queue
-
A. Brodnik, S. Carlsson, J. Karlsson, and J. Munro, "Worst case constant time priority queue," in Proc. 12th Annu. ACM-SIAM Symp. Discrete Algorithms, 2001, pp. 523-528.
-
(2001)
Proc. 12th Annu. ACM-SIAM Symp. Discrete Algorithms
, pp. 523-528
-
-
Brodnik, A.1
Carlsson, S.2
Karlsson, J.3
Munro, J.4
-
39
-
-
0016495233
-
Efficiency of a good but not linear disjoint set union algorithm
-
R. Tarjan, "Efficiency of a good but not linear disjoint set union algorithm," J. ACM, vol. 22, no. 2, pp. 215-225, 1975.
-
(1975)
J. ACM
, vol.22
, Issue.2
, pp. 215-225
-
-
Tarjan, R.1
-
40
-
-
0026103717
-
Automatic average-case analysis of algorithms
-
DOI 10.1016/0304-3975(91)90145-R
-
P. Flajolet, B. Salvy, and P. Zimmermann, "Automatic average-case analysis of algorithms," Theoretical Comput. Sci., vol. 79, no. 1, pp. 37-109, 1991. (Pubitemid 21671631)
-
(1991)
Theoretical Computer Science
, vol.79
, Issue.1
, pp. 37-109
-
-
Flajolet Philippe1
Salvy Bruno2
Zimmermann Paul3
-
41
-
-
0013452612
-
A trivial algorithm whose analysis is not
-
A. T. Jonassen and D. E. Knuth, "A trivial algorithm whose analysis is not," J. Comput. Syst. Sci., vol. 16, no. 3, pp. 301-322, 1978.
-
(1978)
J. Comput. Syst. Sci.
, vol.16
, Issue.3
, pp. 301-322
-
-
Jonassen, A.T.1
Knuth, D.E.2
-
42
-
-
84877914742
-
-
Feb. 12 [Online]
-
GSRC Benchmarks. (2013, Feb. 12) [Online]. Available: http://vlsicad.eecs.umich.edu/BK/GSRCbench/
-
(2013)
GSRC Benchmarks
-
-
-
43
-
-
84877886457
-
-
Feb. 12 [Online]
-
J. Cong and M. Romesis. (2013, Feb. 12). HB Suite [Online]. Available: http://cadlab.cs.ucla.edu/cpmo/HBsuite.html
-
(2013)
HB Suite
-
-
Cong, J.1
Romesis, M.2
-
44
-
-
0742321357
-
Fixed-outline floorplanning: Enabling hierarchical design
-
Dec.
-
S. Adya and I. Markov, "Fixed-outline floorplanning: Enabling hierarchical design," IEEE Trans. VLSI, vol. 11, no. 6, pp. 1120-1135, Dec. 2003.
-
(2003)
IEEE Trans. VLSI
, vol.11
, Issue.6
, pp. 1120-1135
-
-
Adya, S.1
Markov, I.2
-
45
-
-
0002701738
-
Fast evaluation of sequence pair in block placement by longest common subsequence computation
-
X. Tang, R. Tian, and D. F. Wong, "Fast evaluation of sequence pair in block placement by longest common subsequence computation," in Proc. DATE, 2000, pp. 106-111.
-
(2000)
Proc. DATE
, pp. 106-111
-
-
Tang, X.1
Tian, R.2
Wong, D.F.3
-
46
-
-
70449097655
-
The number of symbol comparisons in quicksort and quickselect
-
B. Valĺee, J. Cĺement, J. Fill, and P. Flajolet, "The number of symbol comparisons in quicksort and quickselect," in Proc. Automata, Languages Programm., LNCS 5555. pp. 750-763, 2009.
-
(2009)
Proc. Automata, Languages Programm., LNCS 5555.
, pp. 750-763
-
-
Valĺee, B.1
Cĺement, J.2
Fill, J.3
Flajolet, P.4
|