Modern floorplanning based on B*-tree and fast simulated annealing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 4, 2006, Pages 637-650

  Chen, Tung Chieh ^a,b   Chang, Yao Wen ^a,b,c,d,e,f  

^a IEEE   (United States)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^c WASEDA UNIVERSITY   (Japan)

^d Electronic Design Automation (EDA) Consortium   (Taiwan)

^e Taiwan IC Design Society   (Taiwan)

^f ACM   (Taiwan)

Author keywords

Floorplanning; Physical design

Indexed keywords

BUS-DRIVEN FLOORPLANNING (BDF); FLOORPLANNING; PHYSICAL DESIGN;

ALGORITHMS; CONSTRAINT THEORY; SIMULATED ANNEALING; VLSI CIRCUITS;

TREES (MATHEMATICS);

EID: 33645694781     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.870076     Document Type: Conference Paper

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