-
1
-
-
0346148463
-
On whitespace and stability in mixed-size placement and physical synthesis
-
S.N. Adya, I.L. Markov and P. G. Villarrubia, "On Whitespace and Stability in Mixed-size Placement and Physical Synthesis", ICCAD, 2003, pp. 311-318.
-
(2003)
ICCAD
, pp. 311-318
-
-
Adya, S.N.1
Markov, I.L.2
Villarrubia, P.G.3
-
3
-
-
0036377317
-
-
S.N. Adya and I.L. Markov, "Combinatorial Techniques for Mixed-size Placement", to appear in ACM Trans. on Design Autom. of Elec. Sys., 2004. Also see ISPD 2002, pp. 12-17.
-
ISPD 2002
, pp. 12-17
-
-
-
4
-
-
0742321357
-
Fixed-outline floorplanning: Enabling hierarchical design
-
December
-
S.N. Adya and I.L. Markov "Fixed-outline Floorplanning: Enabling Hierarchical Design", IEEE Trans. on VLSI 11(6), pp. 1120-1135, December 2003. Also see ICCD 2001, pp. 328-334.
-
(2003)
IEEE Trans. on VLSI
, vol.11
, Issue.6
, pp. 1120-1135
-
-
Adya, S.N.1
Markov, I.L.2
-
5
-
-
0742321357
-
-
S.N. Adya and I.L. Markov "Fixed-outline Floorplanning: Enabling Hierarchical Design", IEEE Trans. on VLSI 11(6), pp. 1120-1135, December 2003. Also see ICCD 2001, pp. 328-334.
-
ICCD 2001
, pp. 328-334
-
-
-
7
-
-
2342429765
-
Benchmarking for large-scale placement and beyond
-
S. N. Adya et al., "Benchmarking for Large-Scale Placement and Beyond", IEEE Trans. on CAD 23(4), pp. 472-488, 2004.
-
(2004)
IEEE Trans. on CAD
, vol.23
, Issue.4
, pp. 472-488
-
-
Adya, S.N.1
-
8
-
-
0347409200
-
Fractional cut: Improved recursive bisection placement
-
A. Agnihotri et al., "Fractional Cut: Improved recursive bisection placement", ICCAD, 2003, pp. 307-310.
-
(2003)
ICCAD
, pp. 307-310
-
-
Agnihotri, A.1
-
9
-
-
0036375967
-
An effective congestion driven placement framework
-
U. Brenner and A. Rohe, "An effective congestion driven placement framework", ISPD, 2002, pp. 6-11.
-
(2002)
ISPD
, pp. 6-11
-
-
Brenner, U.1
Rohe, A.2
-
10
-
-
0034313430
-
Optimal partitioners and end-case placers for standard-cell layout
-
A. E. Caldwell, A. B. Kahng, I. L. Markov, "Optimal Partitioners and End-case Placers for Standard-cell Layout", IEEE Trans. on CAD 19(11), pp. 1304-1314, 2000.
-
(2000)
IEEE Trans. on CAD
, vol.19
, Issue.11
, pp. 1304-1314
-
-
Caldwell, A.E.1
Kahng, A.B.2
Markov, I.L.3
-
11
-
-
0033697586
-
Can recursive bisection alone produce routable placements?
-
A. E. Caldwell, A. B. Kahng, I. L. Markov, "Can Recursive Bisection Alone Produce Routable Placements?" DAC 2000, pp. 477-82.
-
(2000)
DAC
, pp. 477-482
-
-
Caldwell, A.E.1
Kahng, A.B.2
Markov, I.L.3
-
13
-
-
0242636372
-
Hierarchical whitespace allocation in top-down placement
-
Nov
-
A. E. Caldwell, A. B. Kahng and I. L. Markov, "Hierarchical Whitespace Allocation in Top-down Placement", IEEE Transactions on CAD 22(11), Nov, 2003, pp. 716-724.
-
(2003)
IEEE Transactions on CAD
, vol.22
, Issue.11
, pp. 716-724
-
-
Caldwell, A.E.1
Kahng, A.B.2
Markov, I.L.3
-
14
-
-
2942641886
-
Floorplanning for throughput
-
M. R. Casu and L. Macchiarulo, "Floorplanning for Throughput", ISPD 2004, pp. 62-69.
-
(2004)
ISPD
, pp. 62-69
-
-
Casu, M.R.1
Macchiarulo, L.2
-
15
-
-
84954416950
-
Multi-level placement for large-scale mixed-size IC designs
-
C.-C. Chang, J. Cong, and X. Yuan, "Multi-level Placement for Large-Scale Mixed-Size IC Designs," ASPDAC 2003, pp. 325-330.
-
(2003)
ASPDAC
, pp. 325-330
-
-
Chang, C.-C.1
Cong, J.2
Yuan, X.3
-
16
-
-
0043092230
-
Microarchitecture evaluation with physical planning
-
J. Cong et al., "Microarchitecture Evaluation With Physical Planning" DAC, 2003, pp. 32-35.
-
(2003)
DAC
, pp. 32-35
-
-
Cong, J.1
-
17
-
-
0031632293
-
Generic global placement and floorplanning
-
H. Eisenmann and F. M. Johannes, "Generic Global Placement and Floorplanning", DAC 1988, p. 269-274.
-
(1988)
DAC
, pp. 269-274
-
-
Eisenmann, H.1
Johannes, F.M.2
-
18
-
-
84860103595
-
-
http://www.faraday-tech.com/StructuredASIC/download.html
-
-
-
-
20
-
-
0033705078
-
Classical floorplanning harmful?
-
A. B. Kahng, "Classical Floorplanning Harmful?", ISPD 2000, pp. 207-213.
-
(2000)
ISPD
, pp. 207-213
-
-
Kahng, A.B.1
-
21
-
-
4444341110
-
Placement feedback: A concept and method for better min-cut placement
-
A. Kahng and S. Reda, "Placement Feedback: A Concept and Method for Better Min-cut Placement", DAC 2004, pp. 357-362.
-
(2004)
DAC
, pp. 357-362
-
-
Kahng, A.1
Reda, S.2
-
22
-
-
0030686036
-
Multilevel hypergraph partitioning: Applications in VLSI domain
-
G. Karypis, R. Aggarwal, V. Kumar and S. Shekhar, "Multilevel Hypergraph Partitioning: Applications in VLSI Domain", DAC 1997, pp. 526-629.
-
(1997)
DAC
, pp. 526-629
-
-
Karypis, G.1
Aggarwal, R.2
Kumar, V.3
Shekhar, S.4
-
23
-
-
0031702566
-
Topology constrained rectilinear block packing for layout reuse
-
M. Z.-W. Kang and W. W.-M. Dai, "Topology Constrained Rectilinear Block Packing For Layout Reuse", ISPD 1998, pp. 179-186.
-
(1998)
ISPD
, pp. 179-186
-
-
Kang, M.Z.-W.1
Dai, W.W.-M.2
-
24
-
-
2942639676
-
Recursive bisection based mixed block placement
-
A. Khatkhate et al., "Recursive Bisection Based Mixed Block Placement", ISPD 2004, pp. 84-89.
-
(2004)
ISPD
, pp. 84-89
-
-
Khatkhate, A.1
-
25
-
-
16244422171
-
Interconnect power dissipation in a microprocessor
-
N. Magen, A. Kolodny, U. Weiser and N. Shamir, "Interconnect Power Dissipation in a Microprocessor", SLIP 2004, pp. 7-13.
-
(2004)
SLIP
, pp. 7-13
-
-
Magen, N.1
Kolodny, A.2
Weiser, U.3
Shamir, N.4
-
26
-
-
0035339227
-
Embedded DRAM development: Technology, physical design, and application issues
-
May
-
D. Keitel-Schulz and N. Wehn, "Embedded DRAM development: Technology, physical design, and application issues", IEEE Design & Test 18(3), pp. 7-15, May 2001.
-
(2001)
IEEE Design & Test
, vol.18
, Issue.3
, pp. 7-15
-
-
Keitel-Schulz, D.1
Wehn, N.2
-
27
-
-
2942659249
-
Design considerations for regular fabrics
-
D. Sherlekar, "Design Considerations for Regular Fabrics," ISPD 2004, pp. 97-102.
-
(2004)
ISPD
, pp. 97-102
-
-
Sherlekar, D.1
-
28
-
-
0030718152
-
Algorithms for large-scale flat placement
-
J. Vygen, "Algorithms for Large-Scale Flat Placement", DAC 1997, pp. 746-751.
-
(1997)
DAC
, pp. 746-751
-
-
Vygen, J.1
-
29
-
-
0031706894
-
Rectilinear block placement using sequence pair
-
J. Xu, P.-N. Guo and C.-K. Cheng, "Rectilinear Block Placement Using Sequence Pair", ISPD 1998, pp. 173-178.
-
(1998)
ISPD
, pp. 173-178
-
-
Xu, J.1
Guo, P.-N.2
Cheng, C.-K.3
-
30
-
-
0001679368
-
MMP: A novel placement algorithm for combined macro-block and standard cell layout design
-
H. Yu, X. Hong and Y. Cai "MMP: A Novel Placement Algorithm for Combined Macro-Block and Standard Cell Layout Design" ASPDAC, 2000, pp. 271-276.
-
(2000)
ASPDAC
, pp. 271-276
-
-
Yu, H.1
Hong, X.2
Cai, Y.3
-
31
-
-
0037387687
-
Routability driven white space allocation for fixed-die standard-cell placement
-
April
-
X. Yang, B.-K. Choi and M. Sarrafzadeh, "Routability Driven White Space Allocation for Fixed-Die Standard-Cell Placement", IEEE Trans. on CAD 22 (4), pp. 410-419, April 2003.
-
(2003)
IEEE Trans. on CAD
, vol.22
, Issue.4
, pp. 410-419
-
-
Yang, X.1
Choi, B.-K.2
Sarrafzadeh, M.3
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