Placement constraints in floorplan design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 7, 2004, Pages 735-745

  Young, Evangeline F Y ^a   Chu, Chris C N ^b   Ho, M L ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^b Iowa State University of Science and Technology   (United States)

Author keywords

Floorplanning; Optimization; Physical design; Placement constraints; Very large scale integration (VLSI) computer aided design (CAD)

Indexed keywords

ALGORITHMS; BENCHMARKING; INPUT OUTPUT PROGRAMS; ITERATIVE METHODS; OPTIMIZATION; ROUTERS; VLSI CIRCUITS;

BOUNDARY CONSTRAINTS; FLOORING; PHYSICAL DESIGN; PLACEMENT CONSTRAINTS; VERY LARGE SCALE INTEGRATION (VLSI) COMPUTER-AIDED DESIGN (CAD);

COMPUTER AIDED DESIGN;

EID: 3142780559     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.830915     Document Type: Conference Paper

References (14)

1. F. Balasa and K. Lampert, "Symmetry within the sequence-pair representation in the context of placement for analog design," IEEE Trans. Computer-Aided Design, vol. 19, pp. 712-731, July 2000.
2. F. Balasa, S. C. Maruvada, and K. Krishnamoorthy, "Efficient solution space exploration based on segment trees in analog placement with symmetry constraints," in Proc. Int. Conf. Computer-Aided Design, 2002, pp. 497-502.
3. Y. C. Chang, Y. W. Chang, G. M. Wu, and S. W. Wu, "B* -trees: A new representation for nonslicing floorplans," in Proc. 37th ACM/IEEE Design Automation Conf., 2000.
4. K. Fujiyoshi and H. Murata, "Arbitrary convex and concave rectilinear block packing using sequence-pair," in Proc. Int. Symp. Physical Design, 1999, pp. 103-110.
5. J. Lai, M.-S. Lin, T.-C. Wong, and L.-C. Wang, "Module placement with boundary constraints using the sequence-pair representation," in Proc. IEEE Asia and South Pacific Design Automation Conf., 2001, pp. 515-520.
6. Y.-Z. Liao and C. K. Wong, "An algorithm to compact a VLSI symbolic layout with mixed constraints," IEEE Trans. Computer-Aided Design, vol. CAD-2, pp. 62-69, Feb. 1983.
7. V. Ma, S. Dong, X. Hong, Y. Cai, C.-K. Cheng, and J. Gu, "VLSI floorplanning with boundary constraints based on comer block list," in Proc. IEEE Asia and South Pacific Design Automation Conf., 2001, pp. 509-514.
8. H. Murata, K. Fujiyoushi, and M. Kaneko, "VLSI/PCB placement with obstacles based on sequence-pair," in Proc. Int. Symp. Physical Design, 1997, pp. 26-31.
9. H. Murata, K. Fujiyoushi, S. Nakatake, and Y. Kajitani, "Rectangle-packing-based module placement," in Proc. IEEE Int. Conf. Computer-Aided Design, 1995, pp. 472-479.
10. X. Tang and D. F. Wong, "Floorplanning with alignment and performance constraints," in Proc. 39th ACM/IEEE Design Automation Conf., 2002, pp. 848-853.
11. T. H. Cormen, C. E. Leiserson, and R. L. Rivest, Introduction to Algorithms. 8th ed. New York: McGraw-Hill, 1992.
12. F. Y. Young and D. F. Wong, "Slicing floorplans with pre-placed modules," in Proc. IEEE Int. Conf. Computer-Aided Design, 1998, pp. 252-258.
13. _, "Slicing floorplans with range constraints." in Proc. Int. Symp. Physical Design, 1999, pp. 97-102.
14. F. Y. Young, D. F. Wong, and H. H. Yang, "Slicing floorplans with boundary constraints," IEEE Trans. Computer-Aided Design, vol. 18, pp. 1385-1389, Sept. 1999.