Corner Sequence - A P-admissible Floorplan Representation with a Worst Case Linear-Time Packing Scheme

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 4, 2003, Pages 679-686

  Lin, Jai Ming ^a,b   Chang, Yao Wen ^c   Lin, Shih Ping ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b REALTEK SEMICONDUCTOR CORP   (Taiwan)

^c NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Floor planning; Layout; Physical design; Placement; VLSI design

Indexed keywords

GRAPH THEORY; MATHEMATICAL MODELS; PLANNING; POLYNOMIALS;

LINEAR-TIME PACKING SCHEMES;

VLSI CIRCUITS;

EID: 0141750617     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.816137     Document Type: Article

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