-
1
-
-
0029488327
-
Rectangle-packing-based module placement
-
H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani: "Rectangle-packing-based module placement," in IEEE ICCAD, pp.472-479, 1995.
-
(1995)
IEEE ICCAD
, pp. 472-479
-
-
Murata, H.1
Fujiyoshi, K.2
Nakatake, S.3
Kajitani, Y.4
-
2
-
-
0031648233
-
VLSI/PCB placement with obstacles based on sequence pair
-
H. Murata, K. Fujiyoshi, and M. Kaneko: "VLSI/PCB placement with obstacles based on sequence pair," IEEE Trans. CAD. vol. 17, no.1, pp.60-68, 1998.
-
(1998)
IEEE Trans. CAD
, vol.17
, Issue.1
, pp. 60-68
-
-
Murata, H.1
Fujiyoshi, K.2
Kaneko, M.3
-
3
-
-
0033885149
-
Arbitrary convex and concave rectilinear block packing using sequence-pair
-
K. Fujiyoshi, and H. Murata: "Arbitrary convex and concave rectilinear block packing using sequence-pair," IEEE Trans. CAD, vol. 19, no.2, pp.224-233, 2000.
-
(2000)
IEEE Trans. CAD
, vol.19
, Issue.2
, pp. 224-233
-
-
Fujiyoshi, K.1
Murata, H.2
-
4
-
-
0003962144
-
An algorithm for finding a maximum weight decreasing sequence in a permutation, motivated by rectangle packing problem
-
VLD96-30, in Japanese
-
T. Takahashi: "An algorithm for finding a maximum weight decreasing sequence in a permutation, motivated by rectangle packing problem," Technical Report IEICE, VLD96-30, pp.31-35, 1996 (in Japanese).
-
(1996)
Technical Report IEICE
, pp. 31-35
-
-
Takahashi, T.1
-
5
-
-
0035670932
-
Fast evaluation of sequence pair in block placement by longest common subsequence computation
-
X. Tang, R. Tian and D.F. Wong: "Fast evaluation of sequence pair in block placement by longest common subsequence computation" IEEE Trans. CAD, vol.20, no.12, pp. 1406-1413, 2001.
-
(2001)
IEEE Trans. CAD
, vol.20
, Issue.12
, pp. 1406-1413
-
-
Tang, X.1
Tian, R.2
Wong, D.F.3
-
6
-
-
84949810913
-
Module placement with boundary constraints using the sequence-pair representation
-
J. Lai, M.-S. Lin, T.-C. Wang, and Li-C. Wang: "Module placement with boundary constraints using the sequence-pair representation," in IEEE ASP-DAC, pp.515-520, 2001.
-
(2001)
IEEE ASP-DAC
, pp. 515-520
-
-
Lai, J.1
Lin, M.-S.2
Wang, T.-C.3
Wang, L.-C.4
-
7
-
-
0030703004
-
A mapping from sequence-pair to rectangular dissection
-
H. Murata, K. Fujiyoshi, T. Watanabe, and Y. Kajitani: "A mapping from sequence-pair to rectangular dissection," in IEEE ASP-DAC, pp.625-633, 1997.
-
(1997)
IEEE ASP-DAC
, pp. 625-633
-
-
Murata, H.1
Fujiyoshi, K.2
Watanabe, T.3
Kajitani, Y.4
-
8
-
-
18544396649
-
Simulated annealing search though general structure floorplans using sequence-pair
-
K. Kiyota, K. Fujiyoshi: "Simulated annealing search though general structure floorplans using sequence-pair," in IEEE ISCAS, pp.III-77-III-80, 2000.
-
(2000)
IEEE ISCAS
, pp. III77-III80
-
-
Kiyota, K.1
Fujiyoshi, K.2
-
9
-
-
0003979360
-
Counting of the topological dissections by reduct-seq representation
-
COMP2000-17
-
K. Sakanushi, and Y. Kajitani, "Counting of the topological dissections by reduct-seq representation," Technical Report IEICE, COMP2000-17, pp.25-32, 2000.
-
(2000)
Technical Report IEICE
, pp. 25-32
-
-
Sakanushi, K.1
Kajitani, Y.2
-
10
-
-
0005497664
-
The quarter-state sequence (Q-sequence) to represent the floorplan and applications to layout optimization
-
K. Sakanushi and Y. Kajitani, "The quarter-state sequence (Q-sequence) to represent the floorplan and applications to layout optimization," in IEEE APCCAS, pp.829-832, 2000.
-
(2000)
IEEE APCCAS
, pp. 829-832
-
-
Sakanushi, K.1
Kajitani, Y.2
-
11
-
-
4243414387
-
Selected sequence-pair
-
VLD2001-17, May, in Japanese
-
C. Kodama and K. Fujiyoshi: "Selected sequence-pair," Technical Report IEICE, VLD2001-17, pp.65-72, May, 2001 (in Japanese).
-
(2001)
Technical Report IEICE
, pp. 65-72
-
-
Kodama, C.1
Fujiyoshi, K.2
-
12
-
-
0013354032
-
Linear time decodable rectangular dissection to represent arbitrary packing using Q-sequence
-
Oct.
-
M. Tsuboi, C. Kodama, K. Sakanushi, K. Fujiyoshi and A. Takahashi "Linear time decodable rectangular dissection to represent arbitrary packing using Q-sequence," in SASIMI, pp.272-278, Oct., 2001.
-
(2001)
SASIMI
, pp. 272-278
-
-
Tsuboi, M.1
Kodama, C.2
Sakanushi, K.3
Fujiyoshi, K.4
Takahashi, A.5
-
13
-
-
13444293789
-
The tight upper bound of the empty rooms in floorplan
-
Oct.
-
Y. Takashima and H. Murata: "The tight upper bound of the empty rooms in floorplan," in SASIMI, pp.264-271, Oct., 2001.
-
(2001)
SASIMI
, pp. 264-271
-
-
Takashima, Y.1
Murata, H.2
-
14
-
-
0344017702
-
An enhanced Q-sequence augmented with essential empty room insertions and parenthesis trees
-
Mar.
-
C. Zhuang, K. Sakanushi, L. Jin and Y. Kajitani: "An enhanced Q-sequence augmented with essential empty room insertions and parenthesis trees," in DATE, pp.61-68, Mar., 2002.
-
(2002)
DATE
, pp. 61-68
-
-
Zhuang, C.1
Sakanushi, K.2
Jin, L.3
Kajitani, Y.4
-
15
-
-
4344678100
-
An efficient decoding method of sequence-pair
-
Oct.
-
C. Kodama and K. Fujiyoshi: "An efficient decoding method of sequence-pair," in IEEE APCCAS, vol.2, pp. 131-136, Oct., 2002.
-
(2002)
IEEE APCCAS
, vol.2
, pp. 131-136
-
-
Kodama, C.1
Fujiyoshi, K.2
-
16
-
-
0036999601
-
An efficient decoding method of sequence-pair with reduced redundancy
-
Dec.
-
C. Kodama and K. Fujiyoshi: "An efficient decoding method of sequence-pair with reduced redundancy," IEICE Trans. Fundamentals, vol.E85-A, no.12, pp.2785-2794, Dec., 2002.
-
(2002)
IEICE Trans. Fundamentals
, vol.E85-A
, Issue.12
, pp. 2785-2794
-
-
Kodama, C.1
Fujiyoshi, K.2
-
17
-
-
84949021500
-
An effective MOVE operation for selected sequence-pair
-
VLD2002-6. May, in Japanese
-
K. Fujiyoshi, C. Kodama and K. Kiyota: "An effective MOVE operation for selected sequence-pair," Technical Report IEICE, VLD2002-6. pp.31-36, May, 2002 (in Japanese).
-
(2002)
Technical Report IEICE
, pp. 31-36
-
-
Fujiyoshi, K.1
Kodama, C.2
Kiyota, K.3
-
18
-
-
0020746257
-
Optimal orientations of cells in slicing floorplan designs
-
L. Stockmeyer: "Optimal orientations of cells in slicing floorplan designs," Info.and Control, vol.57, pp.91-101, 1983.
-
(1983)
Info.and Control
, vol.57
, pp. 91-101
-
-
Stockmeyer, L.1
-
19
-
-
0003108523
-
An optimization technique for integrated circuit layout design
-
T. Ohtsuki, N. Suzigama and H. Hawanishi: "An optimization technique for integrated circuit layout design." Proc. of ICCST, pp.67-68, 1970.
-
(1970)
Proc. of ICCST
, pp. 67-68
-
-
Ohtsuki, T.1
Suzigama, N.2
Hawanishi, H.3
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