-
1
-
-
0742321357
-
Fixed-outline floorplanning: Enabling hierarchical design
-
Dec.
-
S. N. Adya and I. L. Markov. "Fixed-outline floorplanning: Enabling hierarchical design," IEEE Trans. Very Large Scale Integr., vol. 11, no. 6, pp. 1120-1135, Dec. 2003.
-
(2003)
IEEE Trans. Very Large Scale Integr.
, vol.11
, Issue.6
, pp. 1120-1135
-
-
Adya, S.N.1
Markov, I.L.2
-
2
-
-
16244382367
-
Unification of partitioning, placement and floorplanning
-
7C.1, ICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
-
S. N. Adya, S. Chaturvedi, J. A. Roy, D. A. Papa, and I. L. Markov, "Unification of partitioning, placement and floorplanning," in Proc. ICCAD, 2004, pp. 550-557. (Pubitemid 40449287)
-
(2004)
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
, pp. 550-557
-
-
Adya, S.N.1
Chaturvedi, S.2
Roy, J.A.3
Papa, D.A.4
Markov, I.L.5
-
5
-
-
38649107025
-
A new multilevel framework for large-scale interconnect-driven floorplanning
-
DOI 10.1109/TCAD.2007.907065
-
T.-C. Chen, Y.-W. Chang, and S.-C. Lin, "A new multilevel framework for large-scale interconnect-driven floorplanning," IEEE Trans. Comput.-Aided Des., vol. 27, no. 2, pp. 286-294, Feb. 2008. (Pubitemid 351169643)
-
(2008)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.27
, Issue.2
, pp. 286-294
-
-
Chen, T.-C.1
Chang, Y.-W.2
Lin, S.-C.3
-
6
-
-
33645694781
-
*-tree and fast simulated annealing
-
Apr.
-
*-tree and fast simulated annealing," IEEE Trans. Comput.-Aided Des., vol. 25, no. 4, pp. 637-650, Apr. 2006.
-
(2006)
IEEE Trans. Comput.-aided Des.
, vol.25
, Issue.4
, pp. 637-650
-
-
Chen, T.1
Chang, Y.W.2
-
7
-
-
42649135131
-
Fixed-outline floorplanning: Block-position enumeration and a new method for calculating area costs
-
DOI 10.1109/TCAD.2008.917968, 4492827
-
S. Chen and T. Yoshimura, "Fixed-outline floorplanning: Blockposition enumeration and a new method for calculating area costs," IEEE Trans. Comput.-Aided Des., vol. 27, no. 5, pp. 858-871, May 2008. (Pubitemid 351596168)
-
(2008)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.27
, Issue.5
, pp. 858-871
-
-
Chen, S.1
Yoshimura, T.2
-
8
-
-
0036287129
-
Module placement with pre-placed modules using the corner block list representation
-
S. Dhamdhere, N. Zhou, and T.-C. Wang, "Module placement with pre-placed modules using the corner block list representation," in Proc. ISCAS, 2002, pp. 349-352.
-
(2002)
Proc. ISCAS
, pp. 349-352
-
-
Dhamdhere, S.1
Zhou, N.2
Wang, T.-C.3
-
10
-
-
33748097477
-
Fast floorplanning by look-ahead enabled recursive bipartitioning
-
DOI 10.1109/TCAD.2005.859519, 1673746
-
J. Cong, M. Romesis, and J. Shinnerl, "Fast floorplanning by look ahead enabled recursive bipartitioning," IEEE Trans. Comput.-Aided Des., vol. 25, no. 9, pp. 1719-1732, Sep. 2006. (Pubitemid 44304101)
-
(2006)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.25
, Issue.9
, pp. 1719-1732
-
-
Cong, J.1
Romesis, M.2
Shinnerl, J.R.3
-
11
-
-
2942672238
-
An area-optimality study of floorplanning
-
J. Cong, G. Nataneli, M. Romesis, and J. Shinnerl, "An area-optimality study of floorplanning," in Proc. ISPD, 2004, pp. 78-83.
-
(2004)
Proc. ISPD
, pp. 78-83
-
-
Cong, J.1
Nataneli, G.2
Romesis, M.3
Shinnerl, J.4
-
12
-
-
0037702517
-
Constrained modern floorplan-ning
-
Y. Feng, D. P. Mehta, and H. Yang, "Constrained modern floorplan-ning," in Proc. ISPD, 2003, pp. 128-135.
-
(2003)
Proc. ISPD
, pp. 128-135
-
-
Feng, Y.1
Mehta, D.P.2
Yang, H.3
-
13
-
-
0035248720
-
Floorplan-ning using a tree representation
-
Feb.
-
P.-N. Guo, T. Takahashi, C.-K. Cheng, and T. Yoshimura, "Floorplan-ning using a tree representation," IEEE Trans. Comput.-Aided Des., vol. 20, no. 2, pp. 281-289, Feb. 2001.
-
(2001)
IEEE Trans. Comput.-aided Des.
, vol.20
, Issue.2
, pp. 281-289
-
-
Guo, P.-N.1
Takahashi, T.2
Cheng, C.-K.3
Yoshimura, T.4
-
14
-
-
57849111334
-
A novel fixed-outlined floorplanner with zero dead space for hierarchical design
-
O. He, S. Dong, J. Bian, S. Goto, and C.-K. Chen, "A novel fixed-outlined floorplanner with zero dead space for hierarchical design," in Proc. ICCAD, 2008, pp. 16-23.
-
(2008)
Proc. ICCAD
, pp. 16-23
-
-
He, O.1
Dong, S.2
Bian, J.3
Goto, S.4
Chen, C.-K.5
-
15
-
-
0034481271
-
Corner block list: an effective and efficient topological representation of non-slicing floorplan
-
X. Hong, G. Huang, Y. Cai, J. Gu, S. Dong, C.-K. Cheng, and J. Gu, "Corner block list: An effective and efficient topological representation of non-slicing floorplan," in Proc. ICCAD, 2000, pp. 8-12. (Pubitemid 32188488)
-
(2000)
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
, pp. 8-12
-
-
Hong Xianlong1
Huang Gang2
Cai Yici3
Gu Jiangchun4
Dong Sheqin5
Cheng Chung-Kuan6
Gu Jun7
-
17
-
-
31344476295
-
A sweepline algorithm for Euclidean Voronoi diagram of circles
-
DOI 10.1016/j.cad.2005.11.001, PII S0010448505001880
-
L. Jin, D. Kim, L. Mu, D.-S. Kim, and S.-M. Hu, "A sweepline algorithm for Euclidean Voronoi diagram of circules," IEEE Trans. Comput.-Aided Des., vol. 38, no. 3, pp. 260-272, Mar. 2006. (Pubitemid 43144807)
-
(2006)
CAD Computer Aided Design
, vol.38
, Issue.3
, pp. 260-272
-
-
Jin, L.1
Kim, D.2
Mu, L.3
Kim, D.-S.4
Hu, S.-M.5
-
18
-
-
0033705078
-
Classical floorplanning harmful?
-
A. B. Kahng, "Classical floorplanning harmful?" in Proc. ISPD, 2000, pp. 207-213.
-
(2000)
Proc. ISPD
, pp. 207-213
-
-
Kahng, A.B.1
-
19
-
-
26444479778
-
Optimization by simulated annealing
-
S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, "Optimization by simulated annealing," Science, vol. 220, no. 4598, pp. 671-680, 1983.
-
(1983)
Science
, vol.220
, Issue.4598
, pp. 671-680
-
-
Kirkpatrick, S.1
Gelatt, C.D.2
Vecchi, M.P.3
-
20
-
-
2442427516
-
Robust fixed-outline floorplanning through evolutionary search
-
C. Lin, D. Chen, and Y. Wang, "Robust fixed-outline floorplanning through evolutionary search," in Proc. ASP-DAC, 2004, pp. 42-44.
-
(2004)
Proc. ASP-DAC
, pp. 42-44
-
-
Lin, C.1
Chen, D.2
Wang, Y.3
-
21
-
-
13844254630
-
TCG: A transitive closure graph-based representation for general floorplans
-
DOI 10.1109/TVLSI.2004.840760
-
J.-M. Lin and Y.-W. Chang, "TCG: A transitive closure graph based representation for general floorplans," IEEE Trans. Very Large Scale Integr., vol. 13, no. 4, pp. 288-292, Apr. 2005. (Pubitemid 40245516)
-
(2005)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, vol.13
, Issue.2
, pp. 288-292
-
-
Lin, J.-M.1
Chang, Y.-W.2
-
22
-
-
0041940559
-
Applications of second order cone programming
-
Nov.
-
M. S. Lobo, L. Vandenberghe, S. Boyd, and H. Lebret, "Applications of second order cone programming," Linear Algebra Its Applicat., vol. 284, pp. 193-228, Nov. 1998.
-
(1998)
Linear Algebra its Applicat.
, vol.284
, pp. 193-228
-
-
Lobo, M.S.1
Vandenberghe, L.2
Boyd, S.3
Lebret, H.4
-
23
-
-
49549111558
-
Large-scale fixed-outline floorplanning design using convex optimization techniques
-
C. Luo, M. F. Anjos, and A. Vannelli, "Large-scale fixed-outline floorplanning design using convex optimization techniques," in Proc. ASP-DAC, 2008, pp. 198-203.
-
(2008)
Proc. ASP-DAC
, pp. 198-203
-
-
Luo, C.1
Anjos, M.F.2
Vannelli, A.3
-
24
-
-
0030245072
-
Globally optimal floorplanning for a layout problem
-
PII S1057712296068511
-
T.-S. Moh, T.-S. Chang, and S. L. Hakimi, "Globally optimal floor-planning for a layout problem," IEEE Trans. Circuits Syst., vol. 43, no. 9, pp. 713-720, Sep. 1996. (Pubitemid 126777515)
-
(1996)
IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
, vol.43
, Issue.9
, pp. 713-720
-
-
Moh, T.-S.1
Chang, T.-S.2
Louis Hakimi, S.3
-
25
-
-
0029488327
-
Rectangle-packing based module placement
-
H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "Rectangle-packing based module placement," in Proc. ICCAD, 1995, pp. 472-479.
-
(1995)
Proc. ICCAD
, pp. 472-479
-
-
Murata, H.1
Fujiyoshi, K.2
Nakatake, S.3
Kajitani, Y.4
-
26
-
-
0030703025
-
VLSI/PCB placement with obstacles based on sequence-pair
-
H. Murata, K. Fujiyoshi, and M. Kaneko, "VLSI/PCB placement with obstacles based on sequence-pair," in Proc. ISPD, 1997, pp. 26-31.
-
(1997)
Proc. ISPD
, pp. 26-31
-
-
Murata, H.1
Fujiyoshi, K.2
Kaneko, M.3
-
27
-
-
0031651588
-
Sequence-pair based placement method for hard/soft/pre-placed modules
-
H. Murata and E. S. Kuh, "Sequence-pair based placement method for hard/soft/pre-placed modules," in Proc. ISPD, 1998, pp. 167-172.
-
(1998)
Proc. ISPD
, pp. 167-172
-
-
Murata, H.1
Kuh, E.S.2
-
28
-
-
0030408582
-
Module placement on BSG-structure and IC layout applications
-
S. Nakatake, K. Fujiyoshi, H. Murata, and Y. Kajitani, "Module placement on BSG-structure and IC layout applications," in Proc. ICCAD, 1996, pp. 484-491.
-
(1996)
Proc. ICCAD
, pp. 484-491
-
-
Nakatake, S.1
Fujiyoshi, K.2
Murata, H.3
Kajitani, Y.4
-
29
-
-
0032218618
-
Module placement on BSG-structure with pre-placed modules and rectilinear modules
-
S. Nakatake, M. Furuya, and Y. Kajitani, "Module placement on BSG-structure with pre-placed modules and rectilinear modules," in Proc. ASP-DAC, 1998, pp. 571-576.
-
(1998)
Proc. ASP-DAC
, pp. 571-576
-
-
Nakatake, S.1
Furuya, M.2
Kajitani, Y.3
-
30
-
-
85031277343
-
Automatic floorplan design
-
Jun.
-
R. H. J. M. Otten, "Automatic floorplan design," in Proc. DAC, Jun. 1982, pp. 261-267.
-
(1982)
Proc. DAC
, pp. 261-267
-
-
Otten, R.H.J.M.1
-
31
-
-
0026175734
-
Branch-and-bound placement for building block layout
-
H. Onodera, Y. Taniguchi, and K. Tamaru, "Branch-and-bound placement for building block layout," in Proc. DAC, 1991, pp. 433-439.
-
(1991)
Proc. DAC
, pp. 433-439
-
-
Onodera, H.1
Taniguchi, Y.2
Tamaru, K.3
-
32
-
-
0016866389
-
The placement problem as viewed from the physics of classical mechanics
-
N. R. Quinn, Jr., "The placement problem as viewed from the physics of classical mechanics," in Proc. DAC, 1975, pp. 173-178.
-
(1975)
Proc. DAC
, pp. 173-178
-
-
Quinn Jr., N.R.1
-
33
-
-
0018480537
-
A forced directed component placement procedure for printed circuit boards
-
Jun.
-
N. R. Quinn, Jr., and M. A. Breuer, "A forced directed component placement procedure for printed circuit boards," IEEE Trans. Circuits Syst., vol. CAS-26, no. 3, pp. 377-388, Jun. 1979.
-
(1979)
IEEE Trans. Circuits Syst.
, vol.CAS-26
, Issue.3
, pp. 377-388
-
-
Quinn Jr., N.R.1
Breuer, M.A.2
-
35
-
-
85040657895
-
A new algorithm for floorplan design
-
Jun.
-
D. F. Wong and C.-L. Liu, "A new algorithm for floorplan design," in Proc. DAC, Jun. 1986, pp. 101-107.
-
(1986)
Proc. DAC
, pp. 101-107
-
-
Wong, D.F.1
Liu, C.-L.2
-
36
-
-
77649159236
-
DeFer: Deferred decision making enabled fixed-outline floorplanning algorithm
-
Mar.
-
J. Z. Yan and C. Chu, "DeFer: Deferred decision making enabled fixed-outline floorplanning algorithm," IEEE Trans. Comput.-Aided Des., vol. 29, no. 3, pp. 367-381, Mar. 2010.
-
(2010)
IEEE Trans. Comput.-aided Des.
, vol.29
, Issue.3
, pp. 367-381
-
-
Yan, J.Z.1
Chu, C.2
-
37
-
-
0032320583
-
Slicing floorplans with pre-placed modules
-
F. Y. Yong and D. F. Wong, "Slicing floorplans with pre-placed modules," in Proc. ICCAD, 1998, pp. 252-258.
-
(1998)
Proc. ICCAD
, pp. 252-258
-
-
Yong, F.Y.1
Wong, D.F.2
-
38
-
-
0029476187
-
Timing influenced force directed floorplanning
-
H. Youssef, S. M. Sait, and K. J. Al-Farra, "Timing influenced force directed floorplanning," in Proc. Eur. Des. Automat. Conf., 1995, pp. 156-161.
-
(1995)
Proc. Eur. Des. Automat. Conf.
, pp. 156-161
-
-
Youssef, H.1
Sait, S.M.2
Al-Farra, K.J.3
-
40
-
-
33748595788
-
A fixed-die floorplanning algorithm using an analytical approach
-
1594779, Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
-
Y. Zhan, Y. Feng, and S. Sapatnekar, "A fixed-die floorplanning algorithm using an analytical approach," in Proc. ASP-DAC, 2006, pp. 771-776. (Pubitemid 44376024)
-
(2006)
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
, vol.2006
, pp. 771-776
-
-
Zhan, Y.1
Feng, Y.2
Sapatnekar, S.S.3
|