A 247 μw 800 Mb/s/pin DLL-based data self-aligner for through silicon via (TSV) interface

IEEE Journal of Solid-State Circuits

Volumn 48, Issue 3, 2013, Pages 711-723

  Lim, Soo Bin ^a   Lee, Hyun Woo ^a,b   Song, Junyoung ^a   Kim, Chulwoo ^a  

^a Korea University   (South Korea)

^b Hynix Semiconductor Inc   (South Korea)

Author keywords

Calibration; data confliction; deep power down; delay locked loop (DLL); dynamic random access memory (DRAM); GDDR6; half period detector; leakage power; power down; PVT variation; self aligner; self refresh; short current; synchronous mirror delay (SMD); through silicon via (TSV)

Indexed keywords

DATA CONFLICTION; DELAY-LOCKED LOOPS; DYNAMIC RANDOM ACCESS MEMORY; GDDR6; LEAKAGE POWER; POWER DOWNS; PVT VARIATIONS; SELF-ALIGNER; SELF-REFRESH; SYNCHRONOUS MIRROR DELAYS; THROUGH-SILICON-VIA (TSV);

CALIBRATION; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; LEAKAGE CURRENTS;

DATA REDUCTION;

EID: 84874588191     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2013.2242251     Document Type: Article

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