A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAM

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 6, 2002, Pages 726-734

  Kim, Se Jun ^a   Hong, Sang Hoon ^a   Wee, Jae Kyung ^b   Cho, Joo Hwan ^a   Lee, Pil Soo ^a   Ahn, Jin Hong ^a   Chung, Jin Yong ^a  

^a Hynix Semiconductor Inc   (South Korea)

^b Hallym University   (South Korea)

Author keywords

Delay locked loop; Dual loop operation; High speed DRAM; Programmable replica delay; Skew calibration

Indexed keywords

COMPUTER SIMULATION; CORRELATION DETECTORS; DIGITAL FILTERS; DYNAMIC RANDOM ACCESS STORAGE; JITTER; LINEAR NETWORKS; VOLTAGE CONTROL;

DELAY-LOCKED LOOP; DUAL-LOOP OPERATION; HIGH-SPEED DRAM; PROGRAMMABLE REPLICA DELAY; SKEW CALIBRATION;

DELAY CIRCUITS;

EID: 0036612252     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.1004577     Document Type: Article

References (14)

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