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34547322811
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Interconnects in the third dimension: Design challenges for 3D ICs
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San Diego, CA, Jun
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K. Bernstein et al., "Interconnects in the third dimension: Design challenges for 3D ICs," in IEEE DAC'07, San Diego, CA, Jun. 2007, pp. 562-567.
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Bernstein, K.1
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84876920822
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An interconnect-aware methodology for analog and mixed signal design based on high bandwidth (over 40 GHz) on-chip transmission line approach
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DATE02 Conf Paris, France
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Goren, D.1
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On-chip interconnect-aware design and modeling methodology based on high bandwidth transmission line devices
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Study of coplanar transmission lines over the lossy silicon substrate
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presented at the Italy May
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R. Gordin et al., "Study of coplanar transmission lines over the lossy silicon substrate," presented at the SPI'03, Siena, Italy, May 2003.
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SPI'03 Siena
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Gordin, R.1
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84876933496
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Modeling coplanar transmission lines over the lossy silicon substrate
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presented at the SPI'03 May
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D. Goren et al., "Modeling coplanar transmission lines over the lossy silicon substrate," presented at the SPI'03, Siena, Italy, May 2003.
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Siena, Italy
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Goren, D.1
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6
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The closed environment concept in VLSI on-chip transmission lines design and modeling
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D. Goren et al., "The closed environment concept in VLSI on-chip transmission lines design and modeling," presented at the SPI'06, Berlin, Germany, May 2006.
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SPI'06 Berlin
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Goren, D.1
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Predictive high frequency effects of substrate coupling in 3D integrated circuits stacking
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San Francisco, CA, Sep. 28-30
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IEEE Int. Conf. 3D Syst. Integrat. (3DIC 2009)
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Eid, E.1
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Modelling of through silicon via RF performance and impact on signal transmission in 3D integrated circuits
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San Francisco, CA, Sep. 28-30, 2009
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E. Cadix et al., "Modelling of through silicon via RF performance and impact on signal transmission in 3D integrated circuits," in IEEE International Conference on 3D System Integration 3DIC 2009, San Francisco, CA, Sep. 28-30, 2009, pp. 1-7.
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IEEE International Conference on 3D System Integration 3DIC
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Cadix, E.1
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Formulas for the skin effect
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Sep
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Proc. IRE
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Wheeler, H.A.1
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Through-silicon via inductance and capacitance characterization
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Las Vegas, NV, Jun
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Liu, F.1
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A CMOS-compatible process for fabricating electrical through-vias in silicon
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P. S. Andry et al., "A CMOS-compatible process for fabricating electrical through-vias in silicon," presented at the Proc. IEEE 56th Electron. Compon. Technol. Conf., 2006.
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Proc. IEEE 56th Electron. Compon. Technol. Conf
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Andry, P.S.1
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