A 40-550 MHz harmonic-free all-digital delay-locked loop using a variable SAR algorithm

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 2, 2007, Pages 361-373

  Yang, Rong Jyi ^a,b   Liu, Shen Iuan ^a,b  

^a IEEE   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

ADDLL; DCC; Delay locked loop (DLL); Edge combine; Harmonic lock; Successive approximation register (SAR); Variable successive approximation register (VSAR)

Indexed keywords

ADDLL; DELAY-LOCKED LOOP (DLL); EDGE COMBINE; HARMONIC LOCK; SUCCESSIVE APPROXIMATION REGISTER (SAR); VARIABLE SUCCESSIVE APPROXIMATION REGISTER (VSAR);

ALGORITHMS; BANDWIDTH; CLOSED LOOP CONTROL SYSTEMS; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; HARMONIC GENERATION;

DIGITAL CIRCUITS;

EID: 33847728728     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.889381     Document Type: Article

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