A 1.6 v 1.4 Gbp/s/pin consumer DRAM with self-dynamic voltage scaling technique in 44 nm CMOS technology

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 1, 2012, Pages 131-140

  Lee, Hyun Woo ^a,b   Kim, Ki Han ^a   Choi, Young Kyoung ^a   Sohn, Ju Hwan ^a   Park, Nak Kyu ^a   Kim, Kwan Weon ^a   Kim, Chulwoo ^b   Choi, Young Jung ^a   Chung, Byong Tae ^a  

^a Hynix Semiconductor Inc   (South Korea)

^b Korea University   (South Korea)

Author keywords

Adaptive bandwidth delay locked loop(DLL); adaptive clock gating; adaptive design technique; consumer DRAMs; DDR2 SDRAM; dynamic voltage scaling (DVS); frequency aware design; life time; low power design; output enable control; process variation aware design; self reconfigurable design

Indexed keywords

ADAPTIVE CLOCK GATING; ADAPTIVE DESIGNS; CONSUMER DRAMS; DDR2 SDRAM; DELAY-LOCKED LOOPS; DYNAMIC VOLTAGE SCALING (DVS); LIFE-TIMES; LOW-POWER DESIGN; SELF-RECONFIGURABLE; VARIATION-AWARE DESIGN;

BANDWIDTH; CLOCK DISTRIBUTION NETWORKS; CLOCKS; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; DESIGN; JITTER; MICROPROCESSOR CHIPS;

VOLTAGE STABILIZING CIRCUITS;

EID: 84655163337     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2164710     Document Type: Article

References (21)

1. S. Dighe et al., "Within-die variation-aware dynamic-voltage- frequency scaling core mapping and thread hopping for an 80-core processor," in IEEE ISSCC Dig. Tech. Papers, 2010, pp. 174-175.
2. H. W. Lee et al., "A 1.6 V 3.3 Gb/s GDDR3 DRAM with dual-mode phase-and delay-locked loop using power-noise management with unregulated power supply in 54 nm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2009, pp. 140-141.
3. W. J. Yun et al., "A 0.1-to-1.5 GHz 4.2 mW all-digital DLL with dual duty-cycle correction circuit and update gear circuit for DRAM in 66 nm CMOS technology," in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 282-283.
4. D. U. Lee et al., "A 2.5 Gb/s/pin 256 Mb GDDR3 SDRAM with series pipelined CAS latency control and dual-loop digital DLL," in IEEE ISSCC Dig. Tech. Papers, 2006, pp. 547-556.
5. M. Nakai et al., "Dynamic voltage and frequency management for a low-power embedded microprocessor," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 28-35, Jan. 2005.
6. S. Das et al., "RazorII: In situ error detection and correction for PVT and SER tolerance," IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 32-48, Jan. 2009.
7. K. A. Bowman et al., "Energy-efficient and metastability-immune timing-error detection and instruction-replay-based recovery circuits for dynamic-variation tolerance," in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 402-403.
8. T. D. Burd, T. A. Pering, A. J. Stratakos, and R. W. Brodersen, "A dynamic voltage scaled microprocessor system," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1571-1580, Nov. 2000.
9. J. Dorsey et al., "An integrated quad-core opteron processor," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 102-103.
10. T. Fischer, J. Desai, B. Doyle, B. Naffziger, and B. Patella, "A 90-nm variable frequency clock system for a power-managed itanium architecture processor," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 218-228, Jan. 2006.
11. G. Gammie et al., "A 45 nm 3.5 G baseband-and-multimedia application processor usingadaptive body-bias and ultra-low-power techniques," in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 256-257.
12. T. Kuroda et al., "Variable supply-voltage scheme for low-power highspeed CMOS digital design," IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 454-462, Mar. 1998.
13. K. Nowka et al., "A 0.9 V to 1.95 V dynamic voltage-scalable and frequency-scalable 32 b powerPC processor," in IEEE ISSCC Dig. Tech. Papers, 2002, pp. 272-273.
14. N. Sakran, M. Yuffe, M. Mehalel, J. Doweck, E. Knolland, and A. Kovacs, "The implementation of the 65 nm dual-core 64 b MEROM processor," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 106-107.
15. J. Tschanz et al., "Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 292-293.
16. A. Drake et al., "A distributed critical-path timing monitor for a 65 m high-performance microprocessor," in IEEE ISSCC Dig. Tech. Papers, 2007, pp. 389-399.
17. K. Nowka et al., "A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1441-1447, Nov. 2002.
18. ITRS2010 [Online]. Available: http://www.itrs.net/Links/2010ITRS
19. J. Clabes et al., "Design and implementation of the Power5 microprocessor," in IEEE ISSCC Dig. Tech. Papers, 2004, pp. 670-672.
20. R. K. Krishnamurthy, S. K. Mathew, M. A. Anders, S. K. Hsu, H. Kaul, and S. Borkar, "High-performance and low-voltage challenges for sub-45 nm microprocessor circuits," in Proc. Int. Conf. ASIC (ASICON), 2005, pp. 283-286.
21. W.-J. Yun, H.-W. Lee, D. Shin, and S. Kim, "A 3.57 Gb/s/pin low jitter all-digital DLL with dual DCC circuit for GDDR3 DRAM in 54-nm CMOS technology," IEEE Trans. Very Large Scale Integr. Syst., vol. 19, no. 9, pp. 1718-1722, Sep. 2011.