Experimental measurement of a novel power gating structure with intermediate power saving mode

Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Volumn , Issue , 2004, Pages 20-25

  Kim, Suhwan ^a   Kosonocky, Stephen V ^b   Knebel, Daniel R ^b   Stawiasz, Kevin ^b  

^a Seoul National University   (South Korea)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Clock gating; Ground bounce; Inductive noise; Power gating; System on a chip (SOC) design; Wake up latency

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; ELECTRIC SWITCHES; ENERGY DISSIPATION; LEAKAGE CURRENTS; LOGIC CIRCUITS; THRESHOLD VOLTAGE; TRANSISTORS;

CLOCK GATING; GROUND BOUNCE; INDUCTIVE NOISE; SYSTEM-ON-CHIP (SOC) DESIGN; WAKE-UP LATENCY;

VLSI CIRCUITS;

EID: 16244390217     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1013235.1013246     Document Type: Conference Paper

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