A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 48-49

  Lee, Hyun Woo ^a,b   Lim, Soo Bin ^a   Song, Junyoung ^a   Koo, Ja Beom ^a   Kwon, Dae Han ^b   Kang, Jong Ho ^b   Kim, Yunsaing ^b   Choi, Young Jung ^b   Park, Kunwoo ^b   Chung, Byong Tae ^b   Kim, Chulwoo ^a  

^a Korea University   (South Korea)

^b Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS TIME; APPLICATION SYSTEMS; DELAY-LOCKED LOOPS; HIGH-SPEED; HIGH-SPEED OPERATION; MOBILE DRAM; PERFORMANCE VARIATIONS; POWER COSTS; PROCESS VARIATION; READ OPERATION; STACKED DIE;

DATA REDUCTION;

EID: 84860673091     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6176873     Document Type: Conference Paper

References (6)

1. H.-W. Lee et al., "A 1.6V 1.4Gb/s/pin Consumer DRAM with Self-Dynamic Voltage-Scaling Technique in 44nm CMOS Technology," in ISSCC Dig. Tech. Papers, pp. 502-504, Feb. 2011.
2. ITRS2010, [Online];http://www.itrs.net/Links/2010ITRS
3. J.-S. Kim et al., "A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4x128 I/Os using TSV-based stacking," in ISSCC Dig. Tech. Papers, pp. 496-498, Feb. 2011.
4. U. Kang et al., "8Gb 3D DDR3 DRAM using through-silicon-via technology,"in ISSCC Dig. Tech. Papers, pp. 130-131, Feb. 2009.
5. R. J. Yang, and S. I. Liu, "A 40-550 MHz harmonic-free all digital delay locked loop using a variable SAR algorithm," IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 361-373, Feb. 2007.
6. S. Kim, S. V. Kosonocky, D. R. Knebel and K. Stawiasz, "Experimental Measurement of A Novel Power Gating Structure with Intermediate Power Saving Mode," in ISLPED, pp. 20-25, Feb. 2004.