0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 11, 2000, Pages 1680-1689

  Kuge, Shigehiro ^a,c   Kato, Tetsuo ^a,d,e   Furutani, Kiyohiro ^a,f   Kikuda, Shigeru ^a,d   Mitsui, Katsuyoshi ^a,d   Hamamoto, Takeshi ^a,g   Setogawa, Jun ^a   Hamade, Kei ^a   Komiya, Yuichiro ^a   Kawasaki, Satoshi ^a   Kono, Takashi ^a   Amano, Teruhiko ^a   Kubo, Takashi ^a   Haraguchi, Masaru ^a   Nakaoka, Yoshito ^b   Akiyama, Mihoko ^a   Konishi, Yasuhiro ^a   Ozaki, Hideyuki ^a   Yoshihara, Tsutomu ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

^b Daioh Electric   (Japan)

^c KYUSHU UNIVERSITY   (Japan)

^d NAGOYA UNIVERSITY   (Japan)

^e Mitsubishi's ULSI R and D Lab   (Japan)

^f UNIVERSITY OF TOKYO   (Japan)

^g KYOTO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); BIT ERROR RATE; JITTER; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; PHASE LOCKED LOOPS; TUNING;

DELAY LOCKED LOOPS; DOUBLE DATA RATE SYNCHRONOUS DRAM; POST MOLD; REPLICA TUNING; STUB SERIES TERMINATION LOGIC;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0034314917     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.881215     Document Type: Article

References (7)

1. A. Hatakeyama et al., "A 256-Mb SDRAM using a register-controlled digital DLL," in ISSCC Dig. Tech. Papers, 1997, pp. 72-73.
2. S. Eto et al., "A 1-Gb SDRAM with ground-level precharged bit line and nonboosted 2.1-V wordline," in ISSCC Dig. Tech. Papers, 1998, pp. 82-83.
3. J. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1996.
4. T. Kono et al., "A precharged-capacitor-assisted sensing (PCAS) scheme with novel level controller for low-power DRAMs," in Symp. VLSI Circuits Dig. Tech. Papers, 1999, pp. 123-124.
5. M. Johnson and E. Hudson, "A variable delay line PLL for CPU-co-processor synchronization," IEEE J. Solid-State Circuits, vol. 23, pp. 1218-1223, Oct. 1988.
6. M. Saito et al., "Partial response detection technique for driver power reduction in high-speed memory-to-processor communications," in ISSCC Dig. Tech. Papers, 1998, pp. 76-77.
7. M. Tamura et al., "500 Mb/s nonprecharged data bus for high-speed DRAM," in ISSCC Dig. Tech. Papers, 1997, pp. 342-343.