A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 11, 1996, Pages 1656-1665

  Saeki, Takanori ^a,c   Nakaoka, Yuji ^a,d   Fujita, Mamoru ^a,e   Tanaka, Akihito ^a,f   Nagata, Kyoichi ^a   Sakakibara, Kenichi ^a   Matano, Tatsuya ^a   Hoshino, Yukio ^a   Miyano, Kazutaka ^a   Isa, Satoshi ^a   Nakazawa, Shigeyuki ^a   Kakehashi, Eiichiro ^a   Drynan, John Mark ^a   Komuro, Masahiro ^a   Fukase, Tadashi ^a   Iwasaki, Haruo ^a   Takenaka, Motohiro ^a   Sekine, Junichi ^b   Igeta, Masahiko ^b   Nakanishi, Nobuko ^b   Itani, Toshiro ^a   Yoshida, Kazuyoshi ^a   Yoshino, Hiroshi ^a   Hashimoto, Syuichi ^a   Yoshii, Tsuyoshi ^a   Ichinose, Michihiko ^a   Imura, Tomoo ^a   Uziie, Masato ^a   Kikuchi, Shinichi ^b   Koyama, Kuniaki ^a   Fukuzo, Yukio ^a   Okuda, Takashi ^a   more..

^a NEC CORPORATION   (Japan)

^b NEC IC Microcomputer Systems Ltd   (Japan)

^c UNIVERSITY OF TOKYO   (Japan)

^d YAMAGUCHI UNIVERSITY   (Japan)

^e UNIVERSITY OF ELECTRO COMMUNICATIONS   (Japan)

^f TOKAI UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; DELAY CIRCUITS; ELECTRIC CONVERTERS; ELECTRIC CURRENTS; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTOR STORAGE;

PARALLEL SERIAL CONVERTER; PREFETCHED PIPELINE SCHEME; SYNCHRONOUS MIRROR DELAY CIRCUIT;

RANDOM ACCESS STORAGE;

EID: 0030287146     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/jssc.1996.542310     Document Type: Article

References (10)

1. Y. Takai et al., "250 Mbyte/s synchronous DRAM using a 3-stage pipelined architecture," in 1993 Symp. VLSI Circuits, pp. 59-60.
2. S. Lee et al., "A low noise 32 bit-wide 256M synchronous DRAM with column-decoded I/O line," in 1995 Symp. VLSI Circuits, pp. 113-114.
3. H. Yoo et al., "A 150 MHz 8-banks 256M synchronous DRAM with wave pipelining methods," in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 250-251.
4. M. Asakura et al., "A 34 ns 256 Mb DRAM with boosted sense-ground scheme," in ISSCC Dig. Tech. Papers, Feb. 1994, pp. 140-141.
5. T. Saeki et al., "A 2.5 ns clock access 250 MHz 256 Mbit SDRAM with a synchronous mirror delay," in ISSCC Dig. Tech. Papers, Feb. 1996, pp. 374-375.
6. Y. Kodama et al., "A 150-MHz 4-bank 64 M-bit SDRAM with address incrementing pipeline scheme," in 1994 Symp. VLSI Circuits, Dig. Tech. Papers, pp. 81-82.
7. M. Nakamura et al., "A 29 ns 64 Mb DRAM with hierarchical array architecture," in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 245-246.
8. K. Noda et al., "A boosted dual word-line scheme for 256 Mb DRAM's," in 1992 Symp. VLSI Circuits, Dig. Tech. Papers, pp. 112-113.
9. I. A. Young et al., "A PLL clock generator with 5-110 MHz lock range for microprocessors," in ISSCC Dig. Tech. Papers, Feb. 1992, pp. 50-51.
10. T. Lee et al., "A 2.5 V DLL for an 18 Mbit, 500 MB/sec DRAM," in ISSCC Dig. Tech. Papers, Feb. 1994, pp. 300-301.