Skew and jitter suppressed DLL architecture for high frequency DDR SDRAMs

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2000, Pages 76-77

  Hamamoto, Takeshi ^a   Kawasaki, Satoshi ^a   Furutani, Kiyohiro ^a   Yasuda, Kenichi ^a   Konishi, Yasuhiro ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; PHASE COMPARATORS; TIMING CIRCUITS;

DELAYED LOCKED LOOP (DLL) ARCHITECTURE; DOUBLE DATA RATE STATIC DYNAMIC RANDOM ACCESS MEMORY (DDR SDRAM);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0033701277     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)