A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase and delay-locked loop using power-noise management with unregulated in 54nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages

  Lee, Hyun Woo ^a   Yun, Won Joo ^a   Choi, Young Kyoung ^a   Choi, Hyang Hwa ^a   Lee, Jong Jin ^a   Kim, Ki Han ^a   Kang, Shin Deok ^a   Yang, Ji Yeon ^a   Kang, Jae Suck ^a   Lee, Hyeng Ouk ^a   Lee, Dong Uk ^a   Sim, Sujeong ^a   Kim, Young Ju ^a   Choi, Won Jun ^a   Song, Keun Soo ^a   Shin, Sang Hoon ^a   Moon, Hyung Wook ^a   Kwack, Seung Wook ^a   Lee, Jung Woo ^a   Park, Nak Kyu ^a   Kim, Kwan Weon ^a   Choi, Young Jung ^a   Ahn, Jin Hong ^a   Chung, Byong Tae ^a   more..

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349289823     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977347     Document Type: Conference Paper

References (6)

1. J-T. Kwak, C-K. Kown, K-W. Kim, et al., "A Low Cost High Performance Register- Controlled Digital DLL for 1Gbps x32 DDR SDRAM, " IEEE Symp. VLSI Circuits, pp. 283- 284, June 2003.
2. D-U. Lee, H-W. Lee, K-C. Kwean, et al., "A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL, " ISSCC Dig. Tech. Papers, pp. 547-556, Feb. 2006.
3. S-J. Bae, Y-S. Sohn, K-I. Park, et al., "A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques, " ISSCC Dig. Tech. Papers, pp. 278-279, Feb. 2008.
4. W-J. Yun, H-W. Lee, D. Shin, et al., "A 0.1-to-1.5GHz 4.2mW ALL-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology, " ISSCC Dig. Tech. Papers, pp. 282-283, Feb. 2008.
5. F. Gardner, "Charge-pump phase-lock loops, " IEEE Trans. Commun., vol.COM-28, no.11, pp. 1849-1958, Nov. 1980.
6. K-H. Cheng and Y-L. Lo, "A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency-Range Selector for Multiphase Clock Generator, " IEEE Trans. Circuit and Systems II, vol.54, no.7, pp. 561-565, Jul. 2007.