Process-design considerations for three dimensional memory integration

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2009, Pages 60-63

  Iyer, S S ^a   Kirihata, T ^a   Wordeman, M R ^a   Barth, J ^a   Hannon, R H ^a   Malik, R ^a  

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 71049184001     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. U. Kang et al, "8Gb 3D DDR3 DRAM using through Silicon Via Technology" ISSCC Tech. Digest of Papers pp 130-3 (2009)
2. Special Issue of the IBM journal of Research and Development Vol 52 (6) for a collection of papers on 3D technology. (2008)
3. J. Barth et al "A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier" IEEE J. Solid State Circuits V43 (1) pp 86-95 (2008)