Dynamic code duplication with vulnerability awareness for soft error detection on VLIW architectures

Transactions on Architecture and Code Optimization

Volumn 9, Issue 4, 2013, Pages

  Lee, Jongwon ^a   Ko, Yohan ^b   Lee, Kyoungwoo ^b   Youn, Jonghee M ^a   Paek, Yunheung ^a  

^a Seoul National University   (South Korea)

^b Yonsei University   (South Korea)

Author keywords

Code size; Compilerassisted dynamic code duplication scheme; Embedded systems; Physical vulnerability; Soft errors; Temporal vulnerability; VLIW architecture; Vulnerability aware duplication algorithm

Indexed keywords

CODE DUPLICATION; CODE SIZE; PHYSICAL VULNERABILITY; SOFT ERROR; TEMPORAL VULNERABILITY;

ALGORITHMS; EMBEDDED SYSTEMS; ERROR CORRECTION; MICROPROCESSOR CHIPS; SYSTEMS ANALYSIS;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 84872900719     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/2400682.2400707     Document Type: Article

References (44)

1. AHN, M. AND PAEK, Y. 2009. Fast code generation for embedded processors with aliased heterogeneous registers. Trans. high Perform. Embed. Archit. Compilers. 149-172.
2. ASADI, G., SRIDHARAN, V., TAHOORI, M., ANDKAELI, D. 2005. Balancing performance and reliability in the memory hierarchy. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'05). 269-279.
3. AUSTIN, T. 1999. DIVA: A reliable substrate for deep submicron microarchitecture design. In Proceedings of the 32nd Annual International Symposium on Microarchitecture (MICRO'99). IEEE, 196-207.
4. BAUMANN, R. 2005. Soft errors in advanced computer systems. IEEE Des. Test Comput. 22, 3, 258-266.
5. BOLCHINI, C. 2003. A software methodology for detecting hardware faults in vliw data paths. IEEE Trans. Reliabil. 52, 4, 458-468.
6. BORODIN, D. AND JUURLINK, B. H. H. B. 2010. Instruction precomputation with memorization for fault detection. In Proceedings of the Conference on Design, Automation and Test in Europe. 1665-1668.
7. GOMAA, M. AND VIJAYKUMAR, T. 2005. Opportunistic transient-fault detection. In Proceedings of the 32nd International Symposium on Computer Architecture (ISCA'05). IEEE, 172-183.
8. HAZUCHA, P. AND SVENSSON, C. 2000. Impact of cmos technology scaling on the atmospheric neutron soft error rate. IEEE Trans. Nucl. Sci. 47, 6, 2586-2594.
9. HOLM, J. AND BANERJEE, P. 1992. Low cost concurrent error detection in a vliw architecture using replicated instructions. In Proceedings of the International Conference on Parallel Processing. 192-195.
10. HU, J., LI, F., DEGALAHAL, V., KANDEMIR, M., VIJAYKRISHNAN, N., AND IRWIN, M. 2005. Compiler-Directed instruction duplication for soft error detection. In Proceedings of the Conference on Design, Automation and Test in Europe. 1056-1057.
11. HU, J., LI, F., DEGALAHAL, V., KANDEMIR, M., VIJAYKRISHNAN, N., AND IRWIN, M. 2009. Compiler-Assisted soft error detection under performance and energy constraints in embedded systems. ACM Trans. Embed. Comput. Syst. 8, 4, 27.
12. KIM, S. 2006. Area-Efficient error protection for caches. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'06). 1282-1287.
13. LEE, J., YOUN, J., LEE, J., AHN, M., AND PAEK, Y. 2012. Dynamic operands insertion for vliw architecture with a reduced bit-width instruction set. In Proceedings of the 26th International IEEE Parallel Distributed Processing Symposium (IPDPS'12). 119-130.
14. LEE, K., SHRIVASTAVA, A., ISSENIN, I., DUTT, N., AND VENKATASUBRAMANIAN, N. 2006. Mitigating soft error failures for multimedia applications by selective data protection. In Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems. ACM Press, New York, 411-420.
15. LEE, K., SHRIVASTAVA, A., ISSENIN, I., DUTT, N., AND VENKATASUBRAMANIAN, N. 2009. Partially protected caches to reduce failures due to soft errors in multimedia applications. IEEE Trans. VLSI Syst. 17, 9, 1343-1347.
16. LI, S., AHN, J., STRONG, R., BROCKMAN, J., TULLSEN, D., AND JOUPPI, N. 2009. Mcpat: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In Proceedings of the Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'09). IEEE, 469-480.
17. LYONS, D. 2000. Sun screen: Soft error issue in sun enterprise servers. members.forbes.com/global/2000/1113/0323026a.html.
18. MCMAHON, F. H. 1986. The Livermore fortran kernels: A computer test of the numerical performance range. Tech. rep. UCRL-53745, Lawrence Livermore National Laboratory.
19. MIEXNER, A., BAUER, M., AND SORIN, D. 2007. Argus: Low-Cost, comprehensive error detection in simple cores. In Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'07). IEEE, 210-222.
20. MIPS TECHNOLOGY, INC. 2001. MIPS32 Architecture for Programmers. Vol. 1: Introduction to the MIPS32 Architecture. MIPS Technology, Inc., Mountain View, CA.
21. MITRA, S., SEIFERT, N., ZHANG, M., SHI, Q., AND KIM, K. 2005. Robust system design with built-in soft-error resilience. Comput. 38, 2, 43-52.
22. MUCHNICK, S. S. 1997. Advanced Compiler Design and Implementation. Morgan Kaufmann, San Fransisco, CA.
23. MUKHERJEE, S. 2008. Architecture Design for Soft Errors. Morgan Kaufmann, San Fransisco, CA.
24. MUKHERJEE, S., EMER, J., AND REINHARDT, S. 2005. The soft error problem: An architectural perspective. In Proceedings of the 11th International Symposium on High Performance Computer Architecture (HPCA'05). IEEE, 243-247.
25. MUKHERJEE, S., WEAVER, C., EMER, J., REINHARDT, S., AND AUSTIN, T. 2003. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor. In Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'03). IEEE, 29-40.
26. NAKKA, N., PATTABIRAMAN, K., AND IYER, R. 2007. Processor-Level selective replication. In Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks. 544-553.
27. REDDY, V., ROTENBERG, E., AND PARTHASARATHY, S. 2006. Understanding prediction-based partial redundant threading for low-overhead, high-coverage fault tolerance. SIGOPS Oper. Syst. Rev. 40, 83-94.
28. REHMAN, S., SHAFIQUE, M., KRIEBEL, F., AND HENKEL, J. 2011. Reliable software for unreliable hardware: Embedded code generation aiming at reliability. In Proceedings of the 7th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. 237-246.
29. REINHARDT, S. AND MUKHERJEE, S. 2000. Transient fault detection via simultaneous multithreading. SIGARCH Comput. Archit. News 28, 2, 25-36.
30. REIS, G., CHANG, J., AND AUGUST, D. 2007. Automatic instruction-level software-only recovery. IEEE Micro 27, 1, 36-47.
31. REIS, G., CHANG, J., VACHHARAJANI, N., RANGAN, R., AND AUGUST, D. 2005a. Swift: Software implemented fault tolerance. In Proceedings of the International Symposium on Code Generation and Optimization. IEEE, 243-254.
32. REIS, G., CHANG, J., VACHHARAJANI, N., RANGAN, R., AUGUST, D., AND MUKHERJEE, S. 2005b. Software-Controlled fault tolerance. ACM Trans. Archit. Code Optim. 2, 4, 366-396.
33. REIS, G. A., CHANG, J., VACHHARAJANI, N., RANGAN, R., AUGUST, D. I., AND MUKHERJEE, S. S. 2005c. Design and evaluation of hybrid fault-detection systems. In Proceedings of the 32nd Annual International Symposium on Computer Architecture. 148-159.
34. SHRIVASTAVA, A., LEE, J., AND JEYAPAUL, R. 2010. Cache vulnerability equations for protecting data in embedded processor caches from soft errors. SIGPLAN Not. 45, 143-152.
35. SOUNDARARAJAN, N. K., PARASHAR, A., AND SIVASUBRAMANIAM, A. 2007. Mechanisms for bounding vulnerabilities of processor structures. In Proceedings of the 34th Annual International Symposium on Computer Architecture (ISCA'07). ACM Press, New York, 506-515.
36. SYNOPSYS INC. 2001. Design Compiler Reference Manual. Synopsys Inc., Mountain View, CA.
37. TREMBLAY, M. AND TAMIR, Y. 1989. Support for fault tolerance in vlsi processors. In Proceedings of the IEEE International Symposium on Circuits and Systems. IEEE, 388-392.
38. VERA, X., ABELLA, J., CARRETERO, J., AND GONZALEZ, A. 2009. Selective replication: A lightweight technique for soft errors. ACM Trans. Comput. Syst. 27, 4, 8.
39. WANG, N. AND PATEL, S. 2006. Restore: Symptom-Based soft error detection in microprocessors. IEEE Trans. Depend. Secur. Comput. 3, 3, 188-201.
40. WANG, N., QUEK, J., RAFACZ, T., AND PATEL, S. 2004. Characterizing the effects of transient faults on a highperformance processor pipeline. In Proceedings of the International Conference on Dependable Systems and Networks. IEEE, 61-70.
41. WANG, S., HU, J., AND ZIAVRAS, S. 2006. On the characterization of data cache vulnerability in high-performance embedded microprocessors. In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS'06). IEEE, 14-20.
42. WROBEL, F., PALAU, J., CALVET, M., BERSILLON, O., AND DUARTE, H. 2001. Simulation of nucleon-induced nuclear reactions in a simplified sram structure: Scaling effects on seu and mbu cross sections. IEEE Trans. Nucl. Sci. 48, 6, 1946-1952.
43. ZHONG, H., FAN, K., MAHLKE, S., AND SCHLANSKER, M. 2005. A distributed control path architecture for vliw processors. In Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05). IEEE, 197-206.
44. ZIVOJNOVIC, V., VELARDE, J., SCHLAGER, C., ANDMEYR, H. 1994. DSPstone: A dsp-oriented benchmarking methodology. In Proceedings of the International Conference on Signal Processing and Technology.