Mitigating soft error failures for multimedia applications by selective data protection

CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems

Volumn , Issue , 2006, Pages 411-420

  Lee, Kyoungwoo ^a   Shrivastava, Aviral ^b   Issenin, Ilya ^a   Dutt, Nikil ^a   Venkatasubramanian, Nalini ^a  

^a Irvine   (United States)

^b Arizona State University   (United States)

Author keywords

Horizontally partitioned caches; Multimedia embedded systems; Selective data protection; Soft errors

Indexed keywords

BUFFER STORAGE; EMBEDDED SYSTEMS; ENERGY UTILIZATION; MULTIMEDIA SYSTEMS; QUALITY OF SERVICE; SECURITY OF DATA;

ERROR CORRECTION CODE; SELECTIVE DATA PROTECTION; SOFT ERRORS(SE);

ERROR CORRECTION;

EID: 34547230662     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1176760.1176810     Document Type: Conference Paper

References (31)

1. R. Baumann. Soft Errors in Advanced Computer Systems. IEEE Design and Test of Computers, 22(3):258-266, May-June 2005.
2. M. P. Baze, S. P. Buchner, and D. McMorrow. A Digital CMOS Design Technique for SBU Hardening. IEEE Trans. on Nuclear Science, 47(6):2603-2608, Dec 2000.
3. D. Burger and T. M. Austin. The SimpleScalar Tool Set, version 2.0. SIGARCH Computer Architecture News, 25(3):13-25, 1997.
4. Y. Cai, M. T. Schmitz, A. Ejlali, B. M. Al-Hashimi, and S. M. Reddy. Cache Size Selection for Performance, Energy and Reliability of Time-Constrained Systems. In ASP-DAC, 2006.
5. A. Gonz'alez, C. Aliagas, and M. Valero. A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality. In ICS'95, pages 338-347, July 1995.
6. M. Guthaus, J. Ringenberg, D. Ernst, T. Austin, T. Mudge, and R. Brown. MiBench: A Free, Commercially Representative Embedded Benchmark Suite. In Fourth IEEE Workshop Workload Characterization, pages 10-22, Dec 2001.
7. P. Hazucha and C. Svensson. Impact of CMOS Technology Scaling on the Atmospheric Neutron Soft Error Rate. IEEE Trans. on Nuclear Science, 47(6):2586-2594, 2000.
8. Hewlett Packard, http://www.hp.com. HP iPAQ h4000 Series - System Specifications.
9. Intel, http://www.intel.com/design/intelxscale/273473.htm. Intel XScale(R) Core: Developer's Manual.
10. S. Kim. Area-Efficient Error Protection for Caches. In DATE'06, pages 1282-1287, Mar 2006.
11. S. Kim, N. Vijaykrishnan, M. Kandemir, A. Sivasubramaniam, and M. J. Irwin. Partitioned Instruction Cache Architecture for Energy Efficiency. Trans. on Embedded Computing Sys., 2(2):163-185, 2003.
12. C. Lee, M. Potkonjak, and W. H. Mangione-Smith. MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communicatons Systems. In International Symposium on Microarchitecture, pages 330-335, 1997.
13. K. Lee, A. Shrivastava, I. Issenin, N. Dutt, and N. Venkatasubramanian. Horizontally Partitioned Caches to Reduce Failures due to Soft Errors for Mission-Critical Multimedia Embedded Systems. Technical report, UCI, 2006.
14. W. Leung, F.-C. Hsu, and M.-E. Jones. The Ideal SoC Memory: IT-SRAM. In 13th IEEE SoC/ASIC Conference, pages 32-36, Sep 2000.
15. J.-F. Li and Y.-J. Huang. An Error Detection and Correction Scheme for RAMs with Partial-Write Function. In IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05), pages 115-120, 2005.
16. L. Li, V. Degalahal, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. Soft Error and Energy Consumption Interactions: A Data Cache Perspective. In ISLPED, pages 132-137, Aug 2004.
17. R. Mastipuram and E. C. Wee. Soft Errors' Impact on System Reliability. http://www.edn.com/article/CA454636, Sep 2004.
18. S. S. Mukherjee, J. Emer, T. Fossum, and S. K. Reinhardt. Cache Scrubbing in Microprocessors: Myth or Necessity? In PRDC'04, 2004.
19. O. Musseau. Single-Event Effects in SOI Technologies and Devices. IEEE Trans. on Nuclear Science, 43(2):603-613, Apr 1996.
20. G. Neuberger, F. D. Lima, L. Carro, and R. Reis. A Multiple Bit Upset Tolerant SRAM Memory. ACM Trans. on Design Automation of Electronic Systems, 8(4):577-590, Oct 2003.
21. R. Phelan. Addressing Soft Errors in ARM Core-based Designs. Technical report, ARM, 2003.
22. D. K. Pradhan. Fault-Tolerant Computer System Design. Prentice Hall, 1996. ISBN 0-1305-7887-8.
23. J. A. Rivers, E. S. Tam, G. S. Tyson, E. S. Davidson, and M. Farrens. Utilizing Reuse Information in Data Cache Management. In ICS'98, pages 449-456, 1998.
24. P. Roche, G. Gasiot, K. Forbes, Oapos, V. Sullivan, and V. Ferlet. Comparisons of Soft Error Rate for SRAMs in Commercial SOI and Bulk Below the 130-nm Technology Node. IEEE Trans. on Nuclear Science, 50(6):2046-2054, Dec 2003.
25. N. Seifert, D. Moyer, N. Leland, and R. Hokinson. Historical Trend in Alpha-Particle induced Soft Error Rates of the Alpha Microprocessor. In IEEE 39th Annual International Reliability Physics Symposium, 2001.
26. P. Shivakumar and N. Jouppi. CACTI 3.0: An Integrated Cache Timing, Power, and Area Model. In WRL Technical Report 2001/2, 2001.
27. A. Shrivastava, I. Issenin, and N. Dutt. Compilation Techniques for Energy Reduction in Horizontally Partitioned Cache Architectures. In CASES'05, 2005.
28. Synopsys Inc., Mountain View, CA, USA. Design Compiler Reference Manual, 2001.
29. G. Tyson, M. Farrens, J. Matthews, and A. R. Pleszkun. A Modified Approach to Data Cache Management. In MICRO 28, pages 93-103, Los Alamitos, CA, USA, 1995.
30. S. N. University. PeaCE: Ptolemy extension as Codesign Environment. Technical report, SNU, Nov. 2003.
31. F. Wrobel, J. M. Palau, M. C. Calvet, O. Bersillon, and H. Duarte. Simulation of Nucleon-Induced Nuclear Reactions in a Simplified SRAM Structure: Scaling Effects on SEU and MBU Cross Sections. IEEE Trans. on Nuclear Science, 48(6):1946-1952, 2001.