A 62 mV 0.13 μm CMOS standard-cell-based design technique using schmitt-trigger logic

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 1, 2012, Pages 47-60

  Lotze, N ^a   Manoli, Yiannos ^a,b  

^a UNIVERSITY OF FREIBURG   (Germany)

^b HSG IMIT Institute of Micromachining and Information Technology   (Germany)

Author keywords

low power; process variations; Schmitt trigger; Sub threshold; ultra low voltage logic

Indexed keywords

LOW POWER; PROCESS VARIATION; SCHMITT TRIGGER; SUBTHRESHOLD; ULTRALOW VOLTAGE;

DIGITAL DEVICES;

THRESHOLD VOLTAGE;

EID: 84871841633     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2167777     Document Type: Article

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