A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2008, Pages 419-422

  Hwang, Myeong Enn ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUITS; MODULATION; NANOTECHNOLOGY;

6T-SRAM; 90 NM TECHNOLOGIES; CELL STABILITIES; MODULATION TECHNIQUES; PROCESS TOLERANT; PROCESS VARIATIONS; SRAM ARRAYS; STATIC NOISE MARGINS; SUB THRESHOLDS; SUBTHRESHOLD OPERATIONS; SUPPLY VOLTAGES;

STATIC RANDOM ACCESS STORAGE;

EID: 57849166368     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2008.4672109     Document Type: Conference Paper

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