An ultra-low-energy multi-standard JPEG Co-processor in 65 nm CMOS with sub/near threshold upply voltage

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 3, 2010, Pages 668-680

  Pu, Yu ^a   De Gyvez, Jose Pineda ^b   Corporaal, Henk ^c   Ha, Yajun ^d  

^a UNIVERSITY OF TOKYO   (Japan)

^b NXP SEMICONDUCTORS   (Netherlands)

^c EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^d NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

JPEG; Parallel architecture; Sub threshold; Ultra low energy

Indexed keywords

CO-PROCESSORS; CONFIGURABLE; CURRENT DRIVABILITY; DESIGN TECHNIQUE; DIGITAL CONSUMER ELECTRONICS; ENERGY REDUCTION; LOW ENERGIES; MEASUREMENT RESULTS; MULTI-STANDARD; PARALLEL TRANSISTORS; PMOS TRANSISTORS; PROCESSING ENGINE; SELECTION PROCEDURES; STANDARD CELL; SUBTHRESHOLD; SUBTHRESHOLD OPERATION; SUPPLY VOLTAGES; SYSTEM THROUGHPUT; THROUGHPUT DEGRADATION; ULTRA LOW ENERGY;

COSINE TRANSFORMS; DISCRETE COSINE TRANSFORMS; ELECTRIC BATTERIES; ELECTRON ENERGY LOSS SPECTROSCOPY; ENERGY DISSIPATION; ENERGY DISSIPATORS; PARALLEL ARCHITECTURES; THROUGHPUT;

STANDARDS;

EID: 77649112185     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2039684     Document Type: Article

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