A variation-tolerant sub-200 mV 6-T subthreshold SRAM

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 10, 2008, Pages 2338-2348

  Zhai, Bo ^a   Hanson, Scott ^a   Blaauw, David ^a   Sylvester, Dennis ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Low voltage; Subthreshold; Variation tolerant SRAM

Indexed keywords

CMOS INTEGRATED CIRCUITS; LOGIC DESIGN;

BODY BIASSED; CMOS TECHNOLOGIES; ENERGY CONSUMPTIONS; LOW VOLTAGE; MEMORY ARCHITECTURES; MEMORY DESIGNS; SRAM DESIGNS; SUBTHRESHOLD; SUBTHRESHOLD REGIMES; TEST CHIPS; VARIATION-TOLERANT SRAM; VOLTAGE SCALING;

STATIC RANDOM ACCESS STORAGE;

EID: 54049143356     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2001903     Document Type: Conference Paper

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