An energy-efficient noise-tolerant dynamic circuit technique

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 47, Issue 11, 2000, Pages 1300-1306

  Wang, Lei ^a   Shanbhag, Naresh R ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

ASIC; Deep submicron noise; Dynamic circuits; Noise immunity; Noise tolerant circuits

Indexed keywords

ADDERS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; NAND CIRCUITS; RELIABILITY; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

AVERAGE NOISE THRESHOLD ENERGY; DEEP SUBMICRON TECHNOLOGY; DOMINO CIRCUITS; DYNAMIC CIRCUIT TECHNIQUE; NOISE TOLERANCE TECHNIQUE; NOISE TOLERANT DYNAMIC CIRCUIT;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034318561     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.885137     Document Type: Article

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