Cu interconnect limitations and opportunities for SWNT interconnects at the end of the roadmap

IEEE Transactions on Electron Devices

Volumn 60, Issue 1, 2013, Pages 374-382

  Ceyhan, Ahmet ^a   Naeemi, Azad ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Carbon nanotubes (CNTs); high performance computing; interconnections; performance benchmarking; SPICE; subthreshold operation

Indexed keywords

CU INTERCONNECT; ENERGY DELAY PRODUCT; ENERGY-PER-BIT; FUTURE TECHNOLOGIES; GLOBAL LEVELS; HIGH-PERFORMANCE CIRCUITS; HIGH-PERFORMANCE CMOS; HIGH-PERFORMANCE COMPUTING; HISTORICAL TRENDS; INTERCONNECT LATENCY; INTERCONNECT TECHNOLOGY; INTERCONNECTIONS; METAL RESISTIVITY; NANO SCALE; PERFORMANCE BENCHMARKING; PERFORMANCE DEGRADATION; ROADMAP; SIZE EFFECTS; SUBTHRESHOLD OPERATION; TECHNOLOGY SCALING;

CARBON NANOTUBES; COMPUTER SOFTWARE SELECTION AND EVALUATION; DELAY CIRCUITS; PRODUCT DESIGN; SPICE; TECHNOLOGY;

BENCHMARKING;

EID: 84871763696     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2012.2224663     Document Type: Article

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